SiPs for Internet of Things – 3D CIS/IC and MEMS/IC Integration
Most people think that the next big thing after smartphones is the Internet of Things (IoTs). IoTs connect devices for applications such as wearable, car, home, health, etc. with other devices to form a global integrated network and is anticipated to create the next technological revolution. In this study, the key semiconductors and their packaging technologies for IoTs applications will be presented. Emphasis is placed on the 3D CMOS image sensor (CIS) and IC integration and 3D MEMS (Micro-ElectroMechanical System) and IC integration SiPs (system-in-packages). Specifically, for 3D CIS/IC integration SiPs, two cases will be considered; (1) the CIS wafer is stacked on top of the logic/processor wafer by wafer-to-wafer (W2W) bonding and connected through TSVs (through-silicon vias), and (2) the logic/processor chip is chip-to-wafer (C2W) bonded on the CIS wafer with TSVs. For 3D MEMS/IC integration SiPs, three cases will be considered: (1) the MEMS wafer is bonded on the cap wafer (W2W) with TSVs, (2) the MEMS chip is bonded onto a TSV-interposer wafer (C2W), and (3) the MEMS wafer is bonded on the cap wafer with circuits and TSVs (W2W bonding). Their trends will also be discussed.