Embedded Chip Wafer Level Fan-Out Technology

Embedded Chip Wafer Level Fan-Out Technology

Fan-Out Wafer-Level Packaging (FOWLP) is finally beginning to gain traction as a means of packaging semiconductor chips with interconnect densities exceeding the capabilities of standard Wafer Level Chip Scale Packaging (WLCSP).  However, despite its promise, widespread adoption of FOWLP has been limited largely by manufacturing and reliability challenges. In particular, discontinuity at the silicon – mold compound edge leads to numerous issues:  (1) increased panel warpage; (2) mold flash on top of the die surface, which can produce yield loss; (3) a step between the die and the mold compound, which can result in patterning difficulties; and (4) lower reliability, due to the thermal mismatch between the mold compound and the silicon.

This paper describes a fully molded FOWLP technology which addresses the above issues.  In this approach, Cu studs are fabricated at IO locations on the native die surface before the panelization process. Then, during panelization, the die is encased on all sides in mold compound, with the Cu studs providing the current pathways through the mold on the front die surface. Finally, buildup processing is performed on the front panel surface, which consists only of mold compound with exposed Cu studs pads. The benefits of the fully molded structure include: (1) separation of the discontinuity at the die edge from the buildup structure; (2) better panel warpage control due to the balanced molding around the die; and (3) improved board level reliability as a result of the thick mold layer and Cu posts between the chip and PCB connections. The end result is a rugged package. This paper details the fully molded FOWLP technology, describes build examples, and provides reliability data validating the approach.