Enabling Material Solutions for Advanced Electronics Packaging
New packaging technologies for multi-die stacking such as Flip Chip (FC), Wafer-Level Packaging (WLP), and 2.5D/3D-TSV approaches are being used to address key performance issues such as increasing bandwidth, reducing latency (interconnect delay), improving power efficiency, and reducing form factor. With these new technologies come a variety of material and process-related challenges that must be addressed. Equally important to addressing the technical aspects, any new material solutions must also be advantageous from a cost-of-ownership standpoint in order to accelerate adoption into high volume manufacturing. In this talk, new solutions to several of the enabling materials-related challenges will be addressed including but not limited to TSV formation, temporary wafer bonding and debonding, dielectric, lead-free wafer bumping, and Cu pillar.