EDA Challenges on the Road to Node 5
by Debra Vogler, SEMI
The timing of EUVL insertion has been debated and discussed for a number of years. Some experts have expressed the belief that EUVL will be ready for high-volume manufacturing (HVM) in the 2020 timeframe. Development work for the 10nm node has primarily been done using 193 immersion (multi-patterning) lithography, so will it be possible for designs to be backwards compatible should EUVL become available? That is the question SEMI posed to Juan Rey, senior director of Engineering at Mentor Graphics, who will be presenting at SEMICON West 2015 (July 14-16) in San Francisco, Calif.
“If EUV becomes production ready in 2020, then it will be too late for the initial 10nm production tape outs,” Rey told SEMI. “As such, for 10nm, EUV will have to show it is a cost-effective alternative to the most critical layers that currently require several multi-patterning (MP) exposures for immersion. The cost comparison should consider both production costs and the adoption costs due to re-design and new masks.” Rey does not think it is possible at this time to come to a firm conclusion as to the feasibility of complete backwards compatibility. “However, multi-patterning brings very specific requirements on designs that may not be required if EUV supplants MP for all the critical layers. If that is the case, current design restrictions would represent a superset, and one could attain better fidelity, and possibly better performance by using EUV.” Rey explained that because the critical MP layers are primarily in the arena of standard cells and custom IP/design, the industry could expect that these layers are the best candidates for mid-course EUV adoption. “However, we have seen that every exposure technique brings its own restrictions on the design process, which cannot be discounted.”
Other challenges will come into play for the EDA community as the industry goes from node 10 to node 5. Rey noted that EDA suppliers have had to work more closely with IC manufacturers starting at 90nm. “Parasitic extraction and simulation require a more intimate knowledge of the physical characteristics of the process and its design interactions,” said Rey, who will present at the “Scaling Transistors: HVM Solutions Below 14nm; Getting to 5nm” session on July 15 at SEMICON West. “This collaboration resulted in greater direct communication from the early process development with IDMs first, and shortly afterwards with foundries.”
Likewise, Rey explained that close interaction was required earlier with IP providers and leading fabless companies. “At 5nm, exposure challenges and new materials and device/interconnect challenges will require even closer communication.” Though Rey does not believe the current interaction model will have to change, he does believe it will start sooner and will be even more interactive. “Also, process development teams will interact with less ecosystem partners, unlike the days when they passed out a finalized specification to multiple providers for the same solution.” According to Rey, this will result in a level of interaction that will be much deeper, “The process development teams will only be able to engage with a lead partner for each major element.”
Still another consideration for EDA suppliers as the industry drives to 5nm is how to protect manufacturers’ IP. “What we see is that each generation brings tighter requirements on the discrepancies between measured and extracted values,” observed Rey. “For example, in established process nodes, an error band on extraction parameters of 5 percent was sufficient, with 10nm and beyond, however, this error band tightens to 1-2 percent maximum.” He further pointed out that, because of the competitive nature of process development at the advanced nodes, EDA suppliers will be faced with business considerations driven by the manufacturers’ need to protect the details on how those structures are constructed. “This IP protection is in conflict with the need of the EDA tools to use precise and accurate representations in order to achieve the desired error margins.”
In addition to Rey, other experts ─ including An Steegen (imec), Christophe Maleville (Soitec), Raj Jammy (Intermolecular), Harmeet Singh (Lam Research), and Ofer Adan (Applied Materials) ─ will present at the Transistor Scaling session at SEMICON West. Learn more about all the Semiconductor Technology Symposium sessions and register at the SEMICON West 2015 website.
Published with permission; first published in EE Times.
June 30, 2015