CD-SEM Metrology Challenges below 10nm
By Debra Vogler, SEMI
Semiconductor Technology Symposium (STS) sessions on lithography (July 15, 10:00am-12:30pm) and transistor scaling (July 15, 2:00-4:30pm) will be held in conjunction with the upcoming SEMICON West 2015 (July 14-16). These programs will focus on the challenges for high-volume manufacturing at advanced process nodes, including EUV, other lithography strategies, and new wafer processing approaches. In addition, both sessions will feature speakers on the topic of metrology challenges below 10nm. Two speakers from the session, Benjamin Bunday (lithography session) and Ofer Adan (transistor scaling session), were interviewed by SEMI and discussed the need for innovation in CD-SEM metrology as the industry looks ahead from 10nm to 5nm. The lithography session will cover a broad range of issues, including CD-SEM.
CD-SEM: Not Going Away
“There is still a big need for imaging metrology in the fab that isn’t going away,” Benjamin Bunday, project manager, CD Metrology and senior member Technical Staff at SEMATECH, told SEMI. “For a long time, people were talking about scatterometry replacing CD-SEM — no way! They do different things.” While scatterometry provides average profile and CD information, Bunday explained that an imaging tool is still needed to identify what’s there and to measure roughness, variations, shapes, and the like, plus the qualitative information that only images provide.
SEMATECH has been exploring what will be needed for CD-SEM tools going forward and issued a gaps analysis for CD metrology below the 22nm node. The consortium has looked at helium but found that it causes too much physical damage to the surface, and possibly even electrical damage, so that will not be useful in the inline, non-destructive CD metrology role. Bunday noted that while high-voltage SEM (HV-SEM) does improve resolution, in the past, it was found to cause local electrical damage to devices — an important consideration 10 years ago. “Today, however, focused-ion beam (FIB) tools are being used to look at wafers in-line, and they do cause damage to wafers,” commented Bunday. With that in mind, he believes that there might be a role for HV-SEM on sacrificial die or kerf features. “We may be at a point where it is more palatable to accept the damage that can occur with HV-SEM than it was 10 years ago. The industry needs to discuss this.”
Bunday also addressed the CD-SEM resolution challenge facing the industry in the consortium’s gaps analysis paper. “We need significantly improved resolution for the smallest features to reveal the key process details that are required for high-volume manufacturing,” Bunday told SEMI. Figure 1 shows the CD-SEM imaging resolution trend with respect to device dimension scaling and the degree of photoresist shrinkage. According to Bunday, the industry will need to address the meaning of the term “resolution,” which, by itself doesn’t accurately describe all of the other conditions that contribute to the production of a good image, including the size of the probe, interaction volume, as well as material charging and other particle/solid interactions. “There is potential for significant improvement to the existing technology.”
Figure 1. CD-SEM image resolution trend with respect to device dimension scaling and the degree of photoresist shrinkage. The effective resolution means not only resolution, but other competing effects like interaction volume, charging, etc. Note that there is no industry standard methodology for evaluating SEM resolution.
SOURCE: used with permission; Eric Solecky, IBM
CD-SEM: Not Stopping with Top-down Measurement
Ofer Adan, Global Product and Technology manager, Process Diagnostics and Control at Applied Materials, told SEMI that while many of the traditional CD-SEM tools, which measure features from the top down, can be used for about 60 percent of the new devices in 3D logic and memory, but pose problems when trying to measure the high-aspect ratio slits at 3D NAND or the height and sidewall of FinFETs. “If you want to image a FinFET, the gate is not only on top of the fin, but also on both sides of the fin,” explained Adan. “So if you take a top down CD-SEM that you’ve had for 20 years, it uses an electron beam that goes down to the device and returns with a signal, but it cannot detect the dimensions of the sidewall.” These dimensions, which measure the vertical slope of the fin, are critical. Applied Materials recently addressed this challenge with a new CD-SEM tool for performing in-line metrology on 3D devices – both FinFETs and 3D NAND.
An important development in the drive to take CD-SEM measurements beyond the top-down only capability, is the use of tilted electron beam. In a recent SPIE publication, GLOBALFOUNDRIES and Applied Materials were able to show that the use of electronic tilt enabled excellent correlation between measurements obtained using both OCD and AFM tools when measuring FinFETs. “The measurements done using OCD in-scribe, which is the process of record for FinFETs, did not match those measurements taken in-die by CD-SEM using electronic tilt technology,” said Adan (see Figure 2). “We are confident in the CD-SEM in-die measurements as they were correlated with those using an atomic force microscope (AFM).” Even more interesting, according to Adan, is that measurements taken with OCD did not correlate with in-die measurements using the CD-SEM or the AFM. “That’s a potential issue. The industry spends a lot of money on metrology and it does not always get a full return on its investment.”
Figure 2. Tilt beam for fin height: in-die.
SOURCE: Applied Materials. Paper presented at SPIE, “Solving next generation (1x node) metrology challenges using advanced CDSEM capabilities: tilt, high energy and backscatter imaging” by Zhang, Snow, Vaid, and Solecky (GLOBALFOUNDRIES Inc. U.S.); Zhou, Ge, and Yasharzade (Applied Materials, Inc. U.S.); and Shoval, Adan, Schwarzband, and Bar-Zvi (Applied Materials Israel).
Register now for SEMICON West 2015. The Semiconductor Technology Symposium (STS) sessions on Lithography (July 15, 10:00am-12:30pm) will offer expert perspectives from Bunday plus speakers from ASML, Canon Nanotechnologies, CEA Leti, GLOBALFOUNDRIES, Nikon, and Photronics. The Transistor Scaling session offers viewpoints from Adan plus speakers from imec, Intermolecular, Lam Research, Mentor Graphics and Soitec.
June 8, 2015