H.-S. Philip Wong
Department of Electrical Engineering and Center for Integrated Systems
Monolithic 3D Integration of Logic and Memory – The N3XT Frontier
The emerging paradigm of “abundant-data” computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors (projected to surpass a trillion by 2025) and other autonomous sources feeding into “the cloud.” Users will expect to interact with the data and to see trends and relationships in real time. Today’s computing technology cannot scale to satisfy such abundant-data applications with the required throughput and energy efficiency.
The next technology frontier is 3D monolithically integrated chips for abundant-data computing with novel architectures, logic, memory, and embedded thermal management. The key innovation will be an entire non-volatile memory hierarchy, including mass storage, on-chip using fast Magnetoresistive RAM (MRAM) and ultra-dense Resistive RAM (RRAM). Monolithic 3D chips will interleave layers of logic and memory, connecting them with dense interconnects on a scale a million times finer than today’s systems. To remove heat, 3D monolithic chips will contain new embedded cooling technologies, nanomesh-based phase-change structures, and innovative electrical-thermal co-design. This approach will provide Tbytes of fast, non-volatile on-chip storage immersed in thousands of computing elements and will improve system-level energy-delay product by 100-fold. The overall energy-delay product at the system level will therefore improve at least 1,000-fold because of a 10-fold improvement of the extremely scaled logic devices. This 1000-fold improvement in energy-delay product will make it possible to provide the performance of the IBM WATSON in a handheld device.
As an illustration of the exciting opportunity offered by new emerging memories, I will describe recent development of metal oxide resistive switching random access memory (RRAM). RRAM are resistors that can be programmed using relatively moderate voltages (< 3 V), current (< 1 uA), and energy (100 fJ – 1 pJ) in a digital and also analog fashion. RRAM can be integrated with CMOS at the back-end-of-the-line at temperatures below 400C, uses a material set that is familiar to the CMOS fab (e.g. HfO2, Al2O3, TiO2, Ta2O5). It can be programmed many times (> 1E9 cycles even in a university fab). It also has interesting statistical variation properties that can be capitalized for brain-inspired computing.
I will give an overview of on metal oxide resistive switching memory (RRAM). I will go over the fabrication process and essential device characteristics. To facilitate a connection with circuit designers, I will describe a compact model of RRAM. I will describe our efforts to explore device size scaling below 10 nm as well as 3D stacking of RRAM.