Technology Node Transitions Slowing Below 32 nm

Technology Node Transitions Slowing Below 32 nm

By Christian Gregor Dieseldorff, and Clark Tseng, Industry Research & Statistics, SEMI (June 30, 2014)

With the strong growth in the mobile market and their ever increasing functionality, the driver for leading edge semiconductor devices is to reduce power consumption without comprising performance.  The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law. 

The higher cost comes from increasing complexity of leading edge nodes. Among the factors driving complexity are:  an increasing number of new materials integrated onto devices, additional process steps (especially in transistor engineering), and use of multiple patterning in lithography. These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.

SEMI’s World Fab Forecast tracks when technology nodes are phased through R&D, pilot fab, and when introduced in volume fabs.  Over the past ten years, the new data shows a slowing trend below the 32nm technology node when volume production begins.

The data track when a volume fab is capable of producing a technology node based on companies own announcements (each company may have a different definition of volume production).  At the end of 2013, SEMI’s World Fab Forecast shows seven volume fabs with capability at 16/14nm nodes, 25 volume fabs at 25/19nm nodes and 22 volume fabs at 32/28nm nodes.

Introduction of new technology nodes for some product segments follows a two-year cycle (such as seen with MPU). Other product types exhibit a slowing cycle, especially notable for memory. Since the transition from 32/28nm nodes, in 2011-2012, the time to volume production appears to be lengthening.

What’s next?

Many in our industry are grappling with what to do as they have perceived the coming slowdown in technology node transitions.  IC manufacturers are now increasingly looking outside of conventional lithography and wafer size scaling approaches to pick up the pace of cost reduction while increasing transistor density and performance. 

Using memory as an example, to cope with increasing challenges in continuing to scale 2D, memory companies are looking into 3D. The conversion to 3D NAND is slower than scaling of 2D and the cost increases associated with the conversion are more extreme.  Additionally, so far, 3D NAND devices have larger feature sizes than their leading edge 2D counterparts.

For example, with BiCS (Sandisk’s Bit Cost Scaling) there are about 3-4 times more tools needed, more than 4-times additional space in the cleanroom is required, and 2-3 times more time is required for the conversion. Micron estimates that the transition cost per wafer to 3D Generation 1 costs about twice as much than transition cost to 20nm.

Micron expects the market for 3D to ramp in the second half of 2015 and Sandisk plans volume production of their BiCS in 2016. Samsung already began to ramp production of their VNAND (24 layers) mid of 2013.

Companies are also exploring solutions in 3D packaging technology, such as Micron’s Hybrid Memory Cube that was demonstrated in 2013, to continue advance device performance in light of the challenges at leading edge process nodes

What is after 3D for memory companies?

Some companies are looking into ReRAM, a 3D Resistive RAM which enables sub-10nm scaling and new products, while others continue to develop devices based on PCM (Phase Change Memory) approaches.

Used as simply an example of the different thinking being undertaken in keeping pace with Moore’s Law, there are many other innovation areas outside of 3D integration also being pursued.  The technical and business challenges at the leading edge are creating opportunities for new material and substrate solutions, new architectures, new process technologies, and packaging approaches to enable the increases in performance and functionality of electronic systems while addressing economic hurdles of relentlessly reducing the cost per transistor that has long defined our industry.

SEMI World Fab Forecast Report

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2014 and 2015, and learning more about capex for construction projects, fab equipping, technology levels, and products.

The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment. Also check out the Opto/LED Fab Forecast.

Learn more about the SEMI fab databases at:
www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats 

SEMI
www.semi.org
San Jose, California

June 30, 2014