SEMICON West preview - Chip-to-chip optical connections
SEMICON West Preview 2014
Chip-to-Chip Optical Connections Get Close to Market, with Multiple Different Technologies
By Paula Doe, technology director, SEMI
The fast growing demand for bandwidth is driving telecomm and data center user interest in moving high speed optical connections closer and closer to the chips, and recent advances in packaging technology, from microbumping to bonding to wafer-level redistribution now help make it possible.
Chip-to-chip and chip-to-board optical connections increasingly look like a viable solution within the next few years to the input/output roadblock as telecommunication networks and data centers strive to handle the big growth in demand for bandwidth. But there’s still plenty of disagreement on just how to best to make them. We’ve invited some of the leading developers to SEMICON West 2014 this year to discuss their progress towards integrating optics with electronics, both at the package level and the wafer level.
Among the package-level solutions is that of Compass-EOS, who is currently shipping commercial routers with optical connections between the processor chips in the backplane, made by packaging standard optical die in a module with the controlling ASIC. “We don’t do classical silicon photonics, no wave guides or modulators on silicon,” explains Shuki Benjamin, process engineering manager at the Israeli startup, who will speak at the program. “We put conventional VCSELs and photo diode matrices on the silicon, and then take the information in and out of the silicon as light.” The company’s investors include Comcast and Cisco.
The chip assembly technology, developed in collaboration with the Fraunhofer Institute in Berlin, essentially flip chips the optical die to the ASIC with gold pillar bumps, similar to how III-Vs have long been flip-chipped on silicon for military IR detectors for night vision. “We use conventional equipment, but not conventional processes,” says Benjamin.
Analog circuitry included on the processor handles the conversion between optical and electronic signals coming in and out of the chip. The optics-on-ASIC unit is mounted on an organic interposer with a cutout hole to expose the optical dies, and the whole module is then mounted with conventional SMT technology over the cutout in the printed circuit board. There the array of laser and photo diode light pixels are aligned with a matching array of fiber ends in a custom silicon ferrule in the fiber optic bundle. The optical design is a two-lens relay system, where the light coming out of the VCSEL or fiber is collimated in the first lens and then focused in a second into the fiber or photo-diode respectively. This design allows for a very loose tolerance in assembly. A series of these modules creates a full-mesh direct optical link with multimode fibers between multiple processors in the company’s router.
Initial customers are telecommunications network users, including NTT Communications and a Tier 1 telecom player in the US and the Australian system integrator COMDATE, with other users in the US and Japan now testing the equipment. “The main driver is that it allows the system to be smaller and to use less energy,” says Benjamin.
The company is currently doing the wafer-level processing and bumping at a commercial fab, and doing the assembly in house, but looking to move assembly to an OSAT partner to ramp up volume. “Volumes are low to start, since it’s for a router, but as the manufacturing proves itself other applications will arise in big servers that have to move information at high rates,” he suggests. “We believe that in the future more and more dies will have some sort of optical connection to enable high bandwidth data exchange, and we think this technology could help enable it.”
CEA-Leti and partners opt for wafer-level integration
CEA-Leti, on the other hand, bonds the laser material directly to the silicon wafer for processing at the wafer level, and reports state-of-the-art 10% wall-plug efficiency for this hybrid laser on silicon.
“We think we have a very cost effective process,” says Sylvie Menezo, head of the LETI CMOS photonics lab. They grow the laser gain material on an InP substrate, then bond it face down to the silicon wafer with an automated wafer-level process, then remove the InP, and continue to process the laser material islands on silicon in a regular wafer process flow. Putting the expensive compound semiconductor material only where needed saves on cost, as does doing the processing at the wafer level, and potentially re-using the removed InP handle substrate. This photonic chip is then integrated with the electronics with a variant of Leti’s 3D packaging process, flip chipping the driver to the photonics die with tightly pitched bumps. LETI is developing the technology with some heavy-weight partners in communication and network applications within the French state-supported IRT Nanoelec Program under the “Programme Investissements d’Avenir.”
Aurrion takes a somewhat similar approach, building the waveguides and passive optical components directly on the silicon wafer, and then bonding on unprocessed chiplets of higher performance compound semiconductor material for the optical lasers, modulators and photodiodes. The chiplets don’t need to be precisely aligned on the waveguides, as they are etched in the desired patterns in the process flow that follows. Tooling for the die-to-wafer placement and low-temperature bonding have become more and more available from the MEMS and wafer-level –packaging world, which often require redistribution of chips on to a different wafer for packaging. “Leveraging the IC infrastructure allows scaling of III-V-based optical devices such as lasers and modulators up to very large arrays,” says Eric Hall, VP of Business Development at Aurrion, who will also speak at the Silicon Photonics program at SEMICON West 2014.
It remains a challenge to efficient production that the fibers still often have to be actively aligned with the electronics, but the necessary industry infrastructure for some sort of passive and standard connection solution may be starting to appear. Besides developing the laser processing on 200mm CMOS lines, Leti has ported its silicon photonics library from its 200 mm R&D line to its joint 300 mm facility with STMicroelectronics. “It’s reassuring for emergence of silicon photonics that a strong cooperation is established with a semiconductor manufacturer” she notes.
“Telecomm applications will be first, since they can afford the active alignment,” suggests Menezo, noting that commercial transceivers will likely start coming out late this year and next. “Datacom applications will come take a little longer, but with its competitive advantages, photonics will increasingly replace electronics there in perhaps five years.”
These speakers will be joined by Jean Trewhella from IBM, John Cunningham from Oracle, Eric Hall from Aurrion, and Peter de Dobbelaere from Luxtera in the silicon photonics program at SEMICON West 2014, July 8-10, in San Francisco. Visit SEMICON West: http://www.semiconwest.org
Originally published in SemiEngineering.
June 3, 2014
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