How Viable is DSA for Production Lithography in Commercial Semiconductor Fabrication?
Directed Self-Assembly Tutorial to be Featured at SEMI ASMC 2014
by Eric Eisenbraun and Paul Werbaneth
“As line widths drop to 7nm and beyond, EUV may already be outdated. The future there may be directed self-assembly or some other exotic technology that has been ignored for years in the struggle to get EUV working.” (Ed Sperling, in SemiconductorEngineering, 27 February 2014.)
One of the most promising nanolithography techniques now under consideration is Directed Self-Assembly (DSA). In DSA, resists that contain block copolymers are deposited on top of guiding structures which are fabricated on a silicon wafer’s surface using a conventional lithographic technique. Generally, the base layer is comprised of patterned resist, and the DSA layer is a Block Co-Polymer (BCP). The self-directed nature of the BCP assembly process results in very regular, controllable patterns with nanoscale resolution.
The DSA process typically involves a two-step imaging/resist hardening cycle to form the base layer pattern, followed by self-assembly of the BCP, which can be patterned using an oxygen-based reactive ion etch (RIE) process. This results in well-defined nanoscale patterns.
[Source: IBM / SPIE]
To date, 7nm features have been demonstrated with this technique. A major advantage of DSA is that it is relatively low-cost compared to other next-generation lithographic techniques. In addition, a mature toolset and process technologies already exist to support DSA, and the materials are well studied. As such, the prospects for manufacturability are strong.
Increasingly, there are reports from around the world about commercial DSA activity, such this press release from Arkema, France’s leading chemical producer: “Europe launches PLACYD, a large consortium to address Directed Self Assembly (DSA) Lithography.” According to Arkema, the PLACYD consortium of industrial and academic collaborators will establish a dedicated material manufacturing facility that allows the production of block copolymers meeting the rigorous standards required for their use in industry as nanolithographic templates for DSA. Partners in the PLACYD consortium include Applied Materials, ASML, CEA-Leti, Intel, Mentor Graphics, STMicroelectronics, and several European universities and academic research institutions.
PLACYD’s goals are to strengthen the commercial partners’ position in their respective markets, and to secure and accelerate the potential adoption of DSA lithography by the semiconductor industry as a result of being poised to deliver important supply chain components, for example a supply of characterized DSA materials and a proven DSA infrastructure.
At the recent (February 2014) SPIE Advanced Lithography conference held in San Jose, Calif., directed self-assembly was represented front and center, from the keynote talks (“Beyond Scaling: Opportunities and Approaches,” by Akihisa Sekiguchi, Tokyo Electon, Ltd.) to the training courses offered (“Directed Self Assembly and its Application to Nanoscale Fabrication”) through to the conference tracks dedicated to Alternative Lithographic Technologies. Many companies gave DSA-related talks at SPIE, along with universities and research institutes from across the globe.
How viable a candidate then is DSA for production lithography in commercial semiconductor fabrication? As JSR Micro says, “Creating order from disorder. On the order of 10nm. Whatever the horizon brings – double patterning, EUV or DSA, JSR Micro has the solution that is ready to go right now.”
That may be a bit optimistic about the state of DSA in 2014, but to include DSA in the same breath as double patterning and EUV means the semiconductor industry is serious about DSA’s prospects, and likes having another horse enter the advanced photolithography race, whose winner has yet to be crowned.
The upcoming SEMI Advanced Semiconductor Manufacturing Conference 2014 (May 19-21) features a tutorial on directed self-assembly taught by Michael A. Guillorn, Ph.D., research staff member, manager Nanofabrication and Electron Beam Lithography, at the IBM T. J. Watson Research Center. ASMC tutorials have traditionally examined topics just on the horizon of commercialization, and so it is timely that ASMC 2014 offers participants the opportunity to learn more about the very important topic of DSA.
About ASMC 2014: Celebrating 25 years of manufacturing excellence in 2014, the SEMI Advanced Semiconductor Manufacturing Conference continues to fill a critical need in our industry. The conference provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts. The 2014 conference is co-chaired by Israel Ne'eman, Applied Materials and Oliver Patterson, IBM Microelectronics. ASMC 2014 offers keynote talks by Dr. Been-Jon Woo, TSMC, and Dean Freeman, Gartner.
The topical areas ASMC 2014 speakers and poster presenters will address include: 3D/TSV; Advanced Equipment and Materials; Advanced Metrology; Advanced Patterning/Design for Manufacturing; Advanced Process Control (APC); Contamination Free Manufacturing (CFM); Data and Yield Management; Defect Inspection; Equipment Reliability and Productivity Enhancement; Factory Optimization; and Yield Enhancement.
ASMC 2014 also features a panel discussion on “25 Years of Semiconductor Manufacturing: Accomplishments, Current Challenges, Future Directions — From the Internet to the Internet of Things,” with panelists from SEMATECH, RIT, GLOBALFOUNDRIES, Qualcomm, and Applied Materials, and there will be a second tutorial, on Silicon Photonics, taught by Dr. Haisheng Rong, Intel.
ASMC 2014 is being held at the Saratoga Hilton, located in the heart of beautiful, historic Saratoga Springs, New York, just minutes from GLOBALFOUNDRIES Fab 8 in Malta, New York, and just 30 minutes from the Albany International Airport, G450C, SEMATECH, and the College of Nanoscale Science and Engineering.
Eric Eisenbraun is an Associate Professor at the SUNY College of Nanoscale Science and Engineering in Albany, New York.
Paul Werbaneth is a Contributing Editor and member of the Technical Advisory Board at 3D InCites.
March 5, 2014