3D TSV ICs – "We are Ready"
By Werner Schultz, consultant, and Yann Guillou, SEMI Europe
"Application Ready" was an apt theme for the second "European 3D TSV Summit" held January 20 to 22 on the Minatec Campus of CEA Leti in Grenoble, France. With 332 attendees and 24 presenters drawn from a cross section of leading companies in the field, and three keynotes, two panel discussions, and 50 attendees visiting Leti's TSV cleanroom, the 2014 Summit was a clear success and a well-rounded repeat performance of last year's inauguration event. A total of 26 table-top exhibitors were accommodated — with a few more turned away for lack of space.
Raj Pendse, VP and chief marketing officer of STATS Chip Pac, made it a point to add a bit more of definition to the Summit agenda. "We are ready. But the application is not ready." It was a clear “call to arms” for system designers to adopt a more forward looking position on using and implementing 3D TSV ICs in their upcoming projects.
In the near term, this year and next, "economic concerns may limit TSV ramping,” according to Mark Stromberg of market research house Gartner in his market outlook. But he indicated that the unexpected stall would likely be resolved by the beginning of 2015. Another impediment is not likely to go away soon: high capital cost for equipping TSV lines for volume production — which "may limit the number of companies willing and able to implement this promising IC technology." But, Stromberg said, after moving beyond the 10nm node "TSV will become a required technology for system design." This applies especially to MEMS design in high-volume manufacturing, as was discussed at the pre-summit symposium "TSV for MEMS."
A similar stance was taken by Eric Mounier of Yole Developpement in his outlook on "3D Packaging Market Trends and Applications." More specific: the middle end, Mounier predicts, will be a "strategic area", because it is "where foundries, OSATs and IDMs are going to compete." Mounier said "3D ICs will come in a great variety of forms and configurations." TSV/WLP processing already is a reality in camera image sensors. TSV for MEMS already is further along on the road to adoption on a large scale. And, last not least, TSVs are an important enabling technology for future photonic systems.
Speaking from a position of industry leadership in regard to its high-end FPGA process for Xilinx, Mei Kei Ieong of TSMC Europe elevated 3D TSV to the new paradigm for high-density logic besides classical planar scaling guided by Moore's Law: "We are at the leading edge of system scaling." TSMC's CoWoS technology, he says, has the advantage of tightly integrating a multiplicity of chips. "Homogeneous CoWoS is now in production." Heterogeneous setups are at the demonstration stage. A test chip with Wide I/O-1 DRAM has been implemented, the memory interface reaching up to 380MHz. Daisy-chain HBM with six top die on full reticle has been realized as a test vehicle in 2013. For 2014, TSMC plans to tape out and validate a HBM function on CoWoS. "Ultimately we are moving to true 3D stacking with memory on top of logic." When? "This year or next."
"Enabling 2.5D Technology for Commercialisation" was the topic of Michael Thiele's (GlobalFoundries) presentation. With a TSV line installed at the new GloFo fab in Malta, New York, characterized for 20nm and 14nm next in line, and a bump and test facility under construction there, another volume bump and test facility (for SnAg C4 and Cu pillars) already in operation in Dresden, Germany, and a 300mm TSV line for interposer processing installed in Singapore, GloFo appears to be well positioned for 3DTSV — yet strictly focusing on the front side: "We have no plans at the moment for backside processing," Thiele said. "3D integration is a foundry process. We do via middle and will build the necessary capacity for two prospective customers."
The complexity of the 3D TSV supply chain, Thiele said, brings specific requirements for successfully implementing custom designs. First, he said, customers must participate in defining and choosing the supply chain partners. Secondly, transparency and openness is required for sustainable planning and investment. Third, a clear IP ownership definition is needed. And, lastly, Thiele said, there must be systems available across the supply chain for supporting the integration tasks. "Before customers decide on 2.5D TSV they want proof of manufacturability and system level qualification."
Applied Materials was represented at the 2014 TSV Summit by Sesh Ramaswami of the Silicon Systems Group — with a rather optimistic and confident outlook on 3D TSV ICs: "We develop technology platforms to enable TSV and interposers in fan-out extensions for multi-chip integration and panels for lower cost." The fundamental question, according to Ramaswami: "When, specifically with DRAMs, will HVM start delivering ROI to all the members in the supply chain?" Now that the major technology issues have been mostly resolved, Ramaswami said, "The attention is on defects, yields and reliability. This is indicative of a more stable ecosystem and application readiness."
"What is Driving 3D Applications" was the timely question posed by Martin Henry of STMicroelectronics. The answer: imaging, as evidenced by a camera with 2.5D TSV wafer level components in production since 2008. Form factor is the key, he said, with a surface gain of 33 percent and a thickness gain of 50 percent since then. Electronics-to-photonics integration is next. This requires, as Henry stated, TSVs with high aspect ratios and large passive interposers with embedded thermo-mechanical stress sensors in an innovative assembly flow. Advanced logic integration with memory on application processor with via middle was demonstrated in 2012 on 65nm logic and recently on 28nm FDSOI with no impact on BEOL and yield.
Eric Beyne, program director 3D Systems Integration at imec in Leuven, Belgium, presented a detailed cost analysis of 2.5D and 3D system integration. "Wafer thinning, TSV and backside processing are unlike any other processing done before." Key challenge for volume application, Beyne said, is to understand the cost structure and the impact of the various process steps on total cost, and then reduce the cost of integration. Currently, the unfavorable cost situation is exacerbated by the fact that there is no high-volume manufacturing ongoing, which, over time, would involve a cost degression pattern. So the focus has to be on incremental cost improvements — as achieved by incremental technology improvements in all areas. Beyne's conclusion: die stacking offers highest interconnect density at lowest cost, and Cu/oxide Si interposer technology offers the highest circuit density. Despite the fact, as Beyne points out, that it always is an additional cost burden.
A comparison of "2.1D" and 2.5D technologies — and their future market potentials — was provided by Ron Huemoeller of Amkor. "2.1D" works without interposer on a dual or highly integrated organic interposer, offering an RDL focus of 2 – 6µm, with 25 – 30µm pads and 10 – 20µm vias. In his view, both will have their own evolutionary paths and applications in consumer and mobile devices, as well as in high-end graphics processing and servers. Both will take off after 2014 for both logic and HBM. The special advantage of organic interposers, according to Huemoeller, is their embedding of passive components and the reduction of assembly steps, while enlarging interposer size.
A status report on temporary bonding and debonding was presented by Stefan Lutter of Suss MicroTec, defining thin wafer handling as the key enabler of 2.5D and 3D ICs. Lutter described in detail two new processes: a mechanical debonding procedure at room temperature developed by Suss for 3D, using a thin wafer on tape frame, and an excimer laser-assisted debonding method for 2.5D, also at room temperature — which appears to be the general trend.
"Orthogonal Scaling" was the overarching view and sweeping tour d'horizon outlining IBM's "future path for denser and more efficient systems" as presented by Thomas Brunschwiler from IBM Research in Zurich, Switzerland. Three developments, in IBM's view, will define the future of electronic circuits and systems: big data and cognitive computing, the end of classical scaling and materials with their unfavourable energy costs, leading to "orthogonal scaling," with high density provided by TSV connectivity, and circuit proximity provided by stacked memory structures ("hybrid memory cube"). Liquid cooling will enable true volumetric scaling and distributed power delivery, while Si-photonics will provide off-stack communications.
Finally, Patrick Leduc of CEA-Leti gave a brief presentation on "novel architectures for imaging and high-performance energy-efficient computing devices." Leduc stated, "We are in the Zettabyte (1021 Bytes) era." In 2014, data center traffic will reach more than 4 Zettabytes, and the race for more operations per second is pointing towards the Exaflop age. Power supply and heat dissipation in data centers are touching their limits. This, says Leduc, calls for novel interconnect solutions in parallel multi-core computing architectures. They will require appropriate interposer technologies, in other words: active Si interposers with active and passive photonic components integrated in them. His conclusion: "Silicon interposers with 3D and photonics will go ahead for multi-core SoCs, with more than 10 Gbs per link on the 2020 time horizon."
For any enquiries, contact Yann Guillou (email@example.com), European 3D TSV Summit event manager.
For more on 3D TSV, explore the upcoming SEMICON China in March, SEMICON Singapore in April, Advanced Semiconductor Manufacturing Conference (New York) in May, SEMICON West (San Francisco) in July, and SEMICON Europa (Grenoble) in October.
Note: Werner Schulz is a contributing editor to German trade publications PLUS, VDI nachrichten and others.
March 5, 2014