Head of Field Technology
Patrick Martin is the Head of Field Technology for Transistor and Interconnect at Applied Materials, where he is responsible for Logic and Memory Scaling applications. He began his career in 1988 at Texas Instruments holding various positions in process development and integration. For 6 years, Patrick was the Plasma Technology Manager working on TI’s Joint Venture strategy and led a team that built 11 factories worldwide. Upon leaving TI, he spent 8 years in the mask industry exploring fundamental mask to wafer imaging capability. He holds a Master’s Degree in Physics from the University of Illinois Chicago and has numerous patents and publications in Semiconductor Technology.
Conventional scaling approaches that drive semiconductor feature sizes to single digit dimensions are having a dramatic impact on cost affordable scaling especially in the Foundry Segment. The complexity associated with multi-patterning requirements leveraging several passes of lithography exposure with various film deposition and removal techniques now define single layers of the device. Stretched across several critical layers under conventional scaling principles, the value of area scaling is lost to the complexity and cost to achieve area density savings.
Thoughts on device architectural inflections that drive simplification of patterning approaches and their relative impact will be explored and weighed against maintaining the current status quo.