|2016 Conference Agenda and Highlights
|All sessions are held in the Saratoga City Center, except the Welcome and Saratoga Receptions. A complete conference schedule can be downloaded here.
Monday, May 16, 2016
| ||6:30pm-7:30pm ||Welcome Reception and Registration (sponsored by FEI)|
Tuesday, May 17, 2016
| ||7:30-8:30am||Registration/Networking Breakfast (sponsorsed by Nikon Precision) |
| ||8:30-8:45am||Welcome to the Conference (2016 Conference Co-chairs: Dr. Janay Camp/KLA-Tencor and Dr. Jeanne Bickford/GLOBALFOUNDRIES) and 2015 Best Paper Awards |
| ||8:45-9:45am||Keynote: The Economy of Things: How Cognitive IoT Is Driving New Business Models|
| ||Don O'Toole, Business Development Executive, IBM Watson IoT Alliances & Ecosystem Business Development, IBM Corporation (Biography)|
| ||9:45-10:05am||Networking Break (sponsored by AMETEK)|
| ||10:05-12:15pm||Technical Sessions (parallel)|
| || ||Session 1 – Contamination Free Manufacturing (sponsored by Teflon™ fluoroplastic, a brand of the Chemours Company)|
Chairs: Chris Ebert, Linde; Chris Long, IBM Research
Control of contamination on the wafer surface in process is essential to achieving critical rapid yield ramps. This session will feature papers focused on cleaning technologies and wafer handling methods to eliminate contamination and defects from wafer surfaces (top, back, edge) in order to reduce killer defects and drive yield improvement, and minimize/eliminate excursions.
| || ||Session 2 – Advanced Metrology I (sponsored by Metryx, A Lam Research Company)|
Chairs: Amiad Conley, Applied Materials; Ronny Haupt, KLA-Tencor; Alok Vaid, GLOBALFOUNDRIES
Novel processes, complex materials, shrinking process margins are putting significant pressure on measurement tool-sets. As time available to develop upcoming process node/architectures decreases, there is a drive for ever more sophisticated in-line metrology control for fast cycles of learning and process control. This session will cover several key advancements in the field of optical, acoustic & x-ray metrology.
| ||12:15-1:30pm||Networking Lunch|
| ||1:30-3:35pm||Technical Sessions (parallel)|
| || ||Session 3 – Defect Inspection I|
Chairs: Jeffrey Barnum, KLA-Tencor; Oliver Patterson, GLOBALFOUNDRIES
Inline defect inspection continues to enable process optimization and yield improvement. This session will focus on optical defect detection techniques for process systematics, process window discovery and expansion control, EUV reticle print check control, edge defectivity, and diversity sampling to improve defect paretos.
| || ||Session 4 – Factory Optimization I |
Chairs: Dave Gross; Stefan Radloff, Intel Corporation
The challenges of current and future semiconductor process technologies require a higher level of equipment reliability and productivity while improving energy efficiency. Optimizing scenarios and embarking on new approaches for addressing known problems will help improve fab metrics, minimize wafer costs and maximize competitiveness. Presentations in this session will introduce novel ideas for fab and equipment performance improvements and simulation.
| ||3:35-4:00pm||Networking Break (sponsored by Edwards)|
| ||4:00pm||Tutorial: Nanoscale III-V CMOS|
Professor Jesús A. del Alamo, Director, Microsystems Technology Laboratories, Massachusetts Institute of Technology (Biography)
Transistors based on III-V compound semiconductors have emerged as a credible alternative to Si for future nanometer-scale CMOS. This talk will review recent progress as well as challenges confronting III-V electronics in the quest to extend Moore's Law beyond the reach of Si.
| ||5:15-6:45pm||Session 5 – Poster Session (co-sponsored by KLA-Tencor, Marcy Nanocenter at SUNY Polytechnic Institute and Saratoga County Prosperty Partnership)|
Chairs: Jennifer Braggin, Draper Lab; Alan Brightman, Edwards Vacuum; Thanas Budri, Texas Instruments; Larry Hennessy, CH2M Hill; Sophia Keil; Technische Universität Dresden; George Kong, Peregrine Semiconductor; Rama Krishna, Analog Devices; Weimin Li, Entegris; Pinyen Lin, G450C (TSMC); Holly Magoon, Nikon Precision, Inc.; Mohammad Nosrati, Watlow; Leonard Olmer, Micron Technology; Chandar Palamadai, KLA-Tencor; Kirk Peterson, IBM; Thomas Phely-Bobin, Ph.D., Entegris; Jan Rothe, GLOBALFOUNDRIES; Leonard Rubin, Axcelis Technologies; Thomas Sonderman, Rudolph Technologies; Patrick R. Varekamp, GLOBALFOUNDRIES; Charles Weber, Portland State University
Wednesday, May 18, 2016
| ||7:30-8:00am||Registration - City Center Lobby|
| ||8:00-9:00am||Keynote: Advanced Manufacturing… Changing Today’s Paradigm|
Christine Furstoss (Biography)
Vice President and Technical Director, Manufacturing & Materials Technologies
GE Global Research
| ||9:00-9:20am||Networking Break (sponsored by Edwards)|
| ||9:20-11:30am||Technical Sessions (parallel)|
|Session 6 – Defect Inspection II|
Chairs: Israel Ne'eman, Applied Materials; Larry Pulvirent, GLOBALFOUNDRIES
Defect inspection is integral to the development and manufacturing of semiconductor devices. This session will feature papers describing new case studies on utilizing e-beam based technology for in-line defect detection and wafer characterization, tool-to-tool matching and end-of-line Defect Detection.
|Session 7 – Advanced Equipment and Materials Processes|
(sponsored by Air Liquide)
Chairs: Russell Dover, Lam Research; Brett Williams, ON Semiconductor
Advanced memory, analog, and logic manufacturers face daunting challenges as the next generation device nodes come on line. These challenges are being met by the development and applications of innovation in equipment, materials, and processes. This session will focus on and will highlight some of the latest innovations that are being implemented in leading edge high volume and manufacturing.
| ||11:30am-12:25pm||Boxed Lunch|
| ||12:25-2:30pm||Technical Sessions (parallel) |
| || ||Session 8 – Yield Enhancement/Yield Learning|
Chairs: Ishtiaq Ahsan, GLOBALFOUNDRIES; Gary Green, AVOTech; Sagar Kekare, KLA-Tencor
Characterization techniques for driving yield are critical for successful semiconductor manufacturing. This session covers reductions in “dark gate” in metal CMOS processes, preventing gate oxide plasma damage using surface photovoltaic measurements, a novel Al deposition process to minimize power short failures caused by Al whiskers, yield improvements in the nitride stress liner, and an investigation into the transient leakage of point-defects in gate oxides due to phosphorus contaminants.
| || ||Session 9 – Advanced Equipment/CFM|
Chairs: Anand Subramani, KLA-Tencor; David Tucker, Texas Instruments
Advanced memory, analog and logic manufacturers face daunting challenges as the next generation device nodes come on line. These challenges are being met by the development and applications of innovations in equipment, materials, and processes. In this session, we focus on advanced manufacturing concepts ranging from TaN barrier defect reduction to interesting pattern dependent charging effects. We also cover critical aspects and improvements in both front end and back end cleans.
| ||2:30-2:50pm||Networking Break (sponsored by Edwards)|
| ||2:50-4:30pm||Session 10 – Advanced Patterning|
Chairs: Erin Lavigne, GLOBALFOUNDRIES; Jacek Tyminski, Nikon Research
Advanced patterning is a key element of leading-edge semiconductor fabrication. This session contains presentations exploring a range of imaging and design for manufacturing (DFM) techniques employed in IC production. The session highlights virtual metrology, imaging optimization, and the status of 450 mm lithography.
| || ||Session 11 – Advanced Process Control (APC)|
Chairs: Agnes Roussy, EMSE; Raymond van Roijen, GLOBALFOUNDRIES
APC Definition: Advanced Process Control applies virtual metrology, run-to-run control, and big data applications to improve yield and tool availability.
| ||4:45-6:00pm||Panel Discussion: Moore's Law Wall vs. Moore's Wallet, and Where Do We Grow From Here?
Moderator: Paul Werbaneth, Global Product Marketing Director, Intevac (ASMC steering committee)
- Patrick Martin, Head of Field Technology, Transistor and Interconnect, Applied Materials
- Andreas Knorr, Director of Technology Research, GLOBALFOUNDRIES
- David Bloss, Director, Fab Equipment, GSM; Vice President, Technology Manufacturing Group, Intel Corporation
- Bill Miller, Sr. Director of Engineering, Qualcomm
| ||6:30-7:45pm||Saratoga Reception - Canfield Casino (sponsored by Applied Materials, GLOBALFOUNDRIES,Saratoga Economic Development Corp.)|
Thursday, May 19, 20168
| ||8:00am||Registration – City Center Lobby - Floor #2|
| ||8:30-10:20am||Technical Sessions (parallel)|
| || ||Session 12 – Advanced Metrology I|
Chairs: Delphine Le Cunff, STMicroelectronics; Franz Heider, Infineon Technologies
Novel processes, complex materials, shrinking process margins are putting significant pressure on measurement tool-sets. As time available to develop upcoming process node/architectures decreases, there is a drive for ever more sophisticated in-line metrology control for fast cycles of learning and process control. This session will cover several key advancements in the field of patterning metrology and characterization.
| || ||Session 13 – Factory Optimization|
Chairs: Thomas Beeg, GLOBALFOUNDRIES; Eric Eisenbraun, SUNY Polytechnic Institute
The challenges of current and future semiconductor process technologies require a higher level of equipment reliability, quality, repeatability and productivity while improving energy efficiency. Optimizing scenarios and embarking on new approaches for addressing known problems will help improve fab metrics, minimize wafer costs and maximize competitiveness. Presentations in this session will introduce novel strategies to increase the understanding and exploitation of the role played by the process chamber in factory optimization.
| ||9:45-10:05am||Networking Break (Snack Packs provided by Avantor)|
| ||10:05-11:20am||Session 14 – Yield Enhancement|
Chairs: Pratik Joshi, Samsung Austin; Dieter Rathei, DR Yield; Brett Schroeder, Applied Materials
Characterization techniques for driving yield are critical for successful semiconductor manufacturing. Our second session proposes a novel first-metal trench post-lithography rework process for improved yield, an exploration of the correlation between inline electrical yield versus optical inspection at the 14nm node, and methodology for more accurate 3-D capacitance modeling and process variation characterization to enable Moore's Law below 10nm.
| || ||Session 15 – 3D/TSV|
Chairs: James Lu, RPI; Thuy Tran-Quinn, IBM; Russell Dover, Lam Research
This session will cover key innovations in the field of 3D/2.5D/Through-silicon via technology (TSV) technology including TSV processing, underfill, defects and others.
| ||11:25-12:15pm||Keynote: Is China Driving the Urge to Merge?|
| || ||Robert Maire (Biography)|
| ||12:20pm||Closing Remarks.|