Substrate and Interconnect Materials Trends in Packaging

Substrate and Interconnect Materials Trends in Packaging

By Jan Vardaman, TechSearch International, and Dan Tracy, SEMI

The electronics industry trend towards smaller and thinner form factors, coupled with green initiatives and cost reduction efforts, has resulted in many changes in packaging materials. As these trends continue, innovative material solutions will be needed to address emerging requirements related to product integration, mobility, reliability, and performance, according to the SEMI Global Semiconductor Packaging Materials Outlook—2013-2014 Edition. Key semiconductor packaging growth areas include flip chip, ball grid array (BGA), wafer-level packages (WLP), leadframe-based chip scale packages (CSP), stacked-die packages, and system-in-package (SiP)/multichip packages. For the latter, package-on-package (PoP) designs continue to experience strong growth, and Through Silicon Vias (TSV) are being developed to further address requirements for increased integration in 3-D packaging form factors.  The drivers for flip chip packaging continue to be electrical performance, on-chip power distribution, and pad limited designs as these factors, as well as form factor, shift interconnect technology from wire bond to flip chip for processors and devices used in wireless applications. 

For packaging substrates, many high-end devices have migrated from wire bond to flip chip the high-density interconnections on the chip are at a minimum bump array pitch on the substrate of 140 to 150µm for solder bumps in many applications and 40 to 130µm for copper pillar. Bump pitch reductions to 50 to 60µm pitch can be found on company roadmaps corresponding with the introduction of 14nm node silicon. To support these circuit densities the substrates have to be fabricated by the more expensive build-up process, which consists of thermosetting organic films with vias that are laser drilled and circuit patterns formed by a semi-additive process.

According to SEMI, today’s leading-edge CSP substrates have 15µm lines and spaces and are moving toward finer line and spaces, to handle fine bump pitch of ≤110 µm. Substrate vendors are targeting 5µm lines and spaces and 40µm via diameters in the build-up layers in 2015. Core layers are fabricated with12µm lines and spaces with vias as small as 50µm and capture pads as small as 110µm.

Solder balls are an important interconnect material in substrate-based packaging. Most of the solder balls shipping today are lead (Pb)-free, but a few companies still offer tin lead (SnPb) solder balls. High-Pb balls are used to provide improved standoff for packages such as ceramic BGAs, but these packages have small unit volumes.  The most popular Pb-free solder ball composition is the SAC alloy (tin-silver-copper) but a variety of compositions are used in production today. Increasingly, companies have adopted variations of these alloys with small amounts of other elements in the alloy to modify mechanical and physical properties. The solder ball market is forecasted to experience a compound annual growth rate (CAGR) of 9.4 percent in revenues and 11.2 percent in volumes from 2012 through 2017. Approximately 85 percent of solder balls are used for BGAs and CSPs, and 15 percent for WLPs. WLPs typically use ≤300µm diameter solder balls. More information is available on the SEMI website (

While flip chip interconnect continues to see strong growth, wire bonding remains the interconnect choice for many of today’s semiconductor packages.  However, there are many changes underway bonding wire materials. As a result of much development by companies along the bonding wire supply chain, copper wire, including palladium-coated copper (PCC), usage soared as gold metal pricing rose.  In 2013, it is estimated that total copper wire will represent 43 percent of wire shipments, up from less than 2 percent shipped in 2007. Even with the recent drop in gold metal pricing, the industry transition to copper wire is well established and, over the last couple of years, interest in using silver bonding wire has grown as well.

Percentage Share of Wire Shipped by Material Type

SEMI Global semiconductor packaging report 2014

Silver bonding wire usage emerged as a low cost alternative to gold wire without, necessarily, the need for investments in high-end bonding equipment that are required for copper wire. Interest in silver wire developed initially for use in LED packaging and for some memory devices, though usage has ramped in production for other IC devices, such as mobile baseband chips. While advanced packaging has the strongest unit growth rates, it is estimated the wire bonded packages represent 80% or more of the total packaged IC shipments and these packages are estimated to grow at a CAGR of 6 percent through 2017.

All of the information in this article was derived from a recently completed market research study, Global Semiconductor Packaging Materials Outlook—2013-2014 Edition, produced by SEMI and TechSearch International. In developing this report, over 150 in-depth interviews were conducted with semiconductor manufacturers, packaging subcontractors and packaging materials suppliers throughout the world.

TO ORDER YOUR COPY of Global Semiconductor Packaging Materials Outlook—2013-2014 Edition, please contact Dr. Dan P. Tracy, research development director, Industry Research and Statistics, SEMI, via email at, or telephone  1.408.943.7987 or click here for sample, pricing, and ordering information.

January 8, 2014