Test Architecture for Next-Generation NAND Flash
By Ken Hanh Lai, Advantest America, Inc., product marketing manager
Over the next four years, market research firm, IC Insights, forecasts the NAND Flash market to have the third-highest revenue-growth rate among all semiconductor segments as well as stronger bit growth than DRAM. Mobile phones and tablets are driving eMMC volume, pushing faster speeds and transitioning into UFS and other higher speed interfaces. Other applications such as Ultrabooks and enterprise storage solutions are spurring SSD growth, demanding even greater quality and higher speeds for both ONFi and Toggle NAND interfaces.
To keep up with burgeoning market demands, NAND technology is rapidly evolving – in fact, intrinsically shifting. All major NAND manufacturers have begun sub-20nm process migration, further shrinking the basic 2-D NAND memory cell design. Also, more bits are being squeezed into each Flash cell as manufacturers increase from 2-bits-per-cell to 3-bits-per-cell. Recently, Samsung Electronics announced that it is now fabricating 3-bits-per-cell NAND Flash memory devices with 10nm class process technology. Many industry experts believe that 2-D NAND scaling would eventually reach its limit at 10nm process technology. As a result, the industry is adopting novel 3-D NAND lithography processes such as Samsung TCAT, Toshiba BiCS, SK Hynix DC-SF and Macronix BE-SONOS which drastically change the basic memory cell design.
These advances in NAND Flash technology have raised quality and reliability challenges for NAND manufacturers, renewing the need for increased test coverage without hiking up the cost of test and dampening market growth. To deliver the needed performance economically, NAND manufacturers need a test solution with architecture capable of increasing yield and throughput. This paper examines NAND Flash test requirements at the package level and shows how the right ATE architecture can meet them most efficiently.
NAND Flash Needs a Dedicated Test Solution
As with other commodity products, NAND Flash per-bit ASP has been declining dramatically. According to Gartner Dataquest, ASP per Gigabyte of NAND Flash declined from $7,870 in 1997 to just $0.25 in 2012. With the recent industry consolidation, per-bit ASP has stabilized somewhat. Still, Gartner 2Q13 forecast shows a CAGR of -18.7% during 2012-2017. As a result, NAND Flash manufacturers are under constant pressure to reduce cost. One of the ways to reduce cost is to minimize the cost of test. This places the burden on IC manufacturers to utilize the most economical NAND test solution that delivers high throughput and maximizes yield.
A dedicated tester is necessary because NAND Flash requires different test capabilities that are not commonly found on other memory testers. Most importantly, the tester needs to be optimized for NAND Flash testing and should not contain extraneous capabilities which would increase cost. Table 1 summarizes a list of NAND Flash test functions and benefits. Some of these functions will be covered in more detail in this paper.
Click here for PDF of entire paper (11 pages; 12 graphs/charts)
July 1, 2013