Confronting Sub-20nm Front-end Challenges with the “Duck and Weave”
Confronting Sub-20nm Front-end Challenges with the “Duck and Weave”
by Debra Vogler, SEMI
In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers to comment on the challenges they wanted to highlight.
Just as a boxer avoids a surprise shot to the head or torso by using a “duck and weave” maneuver, so to must front-end technologists confront the challenges associated with extending optical lithography while planning for EUV lithography’s eventual high-productivity solution. For the industry, particularly foundries that generally need to handle multiple platforms for a variety of customers — there is the added pile-on arising from developing the two paths to accomplish control of short channel effects and leakage in transistors beyond 20nm, i.e., ultra-thin silicon-over-insulator (SOI)-based technologies and FinFETs. This year’s SEMICON West front-end processing TechXPOTs on lithography (www.semiconwest.org/node/8471) and transistors below 20nm (www.semiconwest.org/node/8481) will provide critical updates on how technologists are coping with these “contenders.” This article takes a look at challenges the industry is facing with commentary from TechXPOT speakers.
Channel Materials: A Progression of SiGe Alloys
Whether an IC manufacturer chooses to make the giant leap to 3D transistors (e.g., the Tri-gate), or takes an evolutionary approach (e.g., using SOI-based technology as a bridge), all roads lead to the implementation of 3D transistor architectures. No matter the path, however, new channel materials will have to be developed. Paul Kirsch, director of the Front-end Process Division at SEMATECH, anticipates that there will be a progressive range of Germanium (Ge) being added to Si – from perhaps 25 percent Ge up to 100 percent Ge — to form channels in pMOS FETs first, followed by nMOS FETs for logic applications. “Industry has a great deal of experience with SiGe already,” notes Kirsch. “It’s understood how to handle that material in the fab and it’s well understood and had good performance benefits in the pMOS FET.” What does need more attention, however, is making SiGe work for the nMOS FET — particularly for contacts and gates. Kirsch further anticipates seeing SiGe entering the roadmap between the 14nm, 10nm, and 7nm nodes, with the possibility that some IC manufacturers could start even sooner than 14nm.
A major hurdle that has to be overcome in the implementation of III-V materials is being able to engineer out the defects from the epitaxial material and the surrounding architecture of the fin to reduce the leakage current. Molecular beam epitaxy (MBE) is too expensive mainly because of its low throughput. This will mean improving what Kirsch says is the preferred process — metalorganic chemical vapor deposition (MOCVD). In addition to engineering out defects, the industry will have to fully understand ESH issues because the source materials for this process are toxic and pyrophoric. “That’s not to say they can’t be understood and handled safely because we have toxic and pyrophoric materials in the fab already, but every process is a little different and attention needs to be given to these materials to make sure that we are handling them very safely,” says Kirsch.
Staying with a Planar Solution
STMicroelectronics’ marketing director of Technology R&D for the Digital Sector, Giorgio Cesana, told SEMI that regardless of the many techniques to extend the technology roadmap, conventional planar bulk technology is reaching its limits. “The last node will be 20nm because it is unable to provide the traditional speed/power gain vs. the 28nm node,” said Cesana. To continue to follow the Moore’s Law roadmap, the industry has developed new techniques to produce fully-depleted transistors that overcome traditional bulk planar limits. There are two possibilities: stay on a planar (2D) transistor structure obtaining fully-depleted devices using a thin SOI substrate, or move to FinFET 3D structures.
“STMicroelectronics has opted for the planar solution built on a thin silicon film above a thin buried oxide layer, which is simpler to manufacture while still offering the same fully-depleted benefits,” explained Cesana. With the company’s 28nm FD-SOI node in production, it is now focusing on the development of the next node. “At 14nm, this will implement a set of new features for further increasing performances while optimizing power consumption and operating at reduced voltage levels.”
Test and Diagnosis at 16/14nm and Beyond
As the industry moves to 3D transistor architectures, Joe Sawicki, VP and GM of the Design-to-Silicon Division at Mentor Graphics, observes that at 16/14nm, “You’re not just dealing with scaling, you’re dealing with fundamental changes in the transistor and cell architectures. How defects will manifest themselves and behave in these new architectures is still an unknown.” The key, he pointed out, is going after potential defects at the transistor level using a test generation technology that looks into the standard cell itself (i.e., cell-aware automatic test pattern generation (ATPG)). “Unlike the standard test pattern generation used today that just looks at the logical boundary of the cell and tries to ensure that all the interconnects are wired correctly, cell-aware ATPG takes that one step further by looking into the standard cell transistor structures to test and ensure that all the individual transistors and the connections between them are functional.”
Though defects that might be unique to FinFET structures below 16nm are still to be determined, Sawicki explains that cell-aware ATPG is capable of defining both static and dynamic fault models on the transistor structures, as well as on the cell-internal interconnect. “It has already been successful in finding defects at other nodes that the traditional fault models miss,” said Sawicki.
As cell-aware testing goes from 20nm to 14nm, Sawicki anticipates that the only evolution in going to the next node will be in the SPICE level model characterization to create the initial cell-aware fault models. “Defects in FinFET transistors may cause different behaviors and require slightly different fault models to detect them,” said Sawicki. “Since the cell-aware technology starts with a transistor level cell characterization step to create the fault model, it’s expected that from a usage and ATPG process point of view, there should be little additional evolution to the technology for FinFET technology.”
Learn more about front-end challenges at SEMICON West 2013 and hear from the experts — live! Your registration includes free access to the exhibition hall plus all TechXPOT sessions, keynotes and executive panels.
Register for SEMICON West through May 10 at no charge: www.semiconwest.org/register.
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