What Is Computational Lithography and How Does It Keep Moore’s Law Alive?

What Is Computational Lithography and How Does It Keep Moore’s Law Alive?

By Paul Werbaneth, ASMC Steering Committee

Attend ASMC 2013

May 13-16 -- Saratoga Springs, New York


Subramani Kengeri, GLOBALFOUNDRIES
Tim Hendry, Intel Corporation
Bill McClean, IC Insights

Tutorials: Computational Lithography; 3D-ICs
Panel: "Supersize Me" (450mm wafers)

Plus technical sessions! 

ASMC websitewww.semi.org/asmc2013
PDF agenda: Complete ASMC schedule

Historically, semiconductor device scaling was enabled by the continuous development and implementation of optical lithography innovations — starting from early mask aligner processes through to the 193nm immersion lithography schemes employed in High Volume Manufacturing today.  

It’s been said many times along the way that the limits of optical lithography are “just around the corner,” necessitating the introduction of new, potentially disruptive lithography technologies in order to maintain the steady course of process node shrinks that productively keeps the semiconductor industry on its Moore’s Law course.

One such disruptive next-generation lithography technology “just around the optical lithography corner” is EUV Lithography, the subject of intense research and development efforts among lithography equipment suppliers, material suppliers, and semiconductor device makers. Many  hoped that implementation of next-generation lithography technology using EUVL would occur at the 28nm process node, but that milestone was missed, and it appears likely now that EUVL won’t be deployed until the 10nm process node, if then, despite best efforts and earnest desires by the entire advanced semiconductor manufacturing community.

Putting EUVL technology into commercial production is not easily accomplished, as the shift to EUVL requires substantial and revolutionary changes from today’s standard photolithography process modules, and the magnitude of these changes are unprecedented  in the history of the semiconductor industry.

Until EUVL technology is available for practical use, computational lithography continues to be relied upon as, the required core technology solution to extending optical lithography, and with it, Moore’s Law, into the 20nm, and sub-20nm manufacturing regimes.

One expert well-versed on the subject of computational lithography is Chris Mack. Mack developed the lithography simulation software PROLITH as the founder of FINLE Technologies, and also served as VP of Lithography Technology for KLA-Tencor. He received the 2003 SEMI Award for North America for his efforts in lithography simulation and education.

According to Dr. Mack, computational lithography is an umbrella term that covers the application of computationally-intensive physical and empirical models, based on the physics of electromagnetic radiation diffraction and interference effects, and the chemistry of photoresists, to predict and optimize semiconductor device feature patterning.

Physics-based rigorous modeling has been used for nearly 40 years to develop new lithography processes and optimize existing ones.

Optical Proximity Correction (OPC) is one of the image enhancement techniques that nestles under the computational lithography umbrella. From its early development more than 20 years ago, OPC became an essential contributor to Moore’s Law progress at the 250nm process node and beyond, says Dr. Mack.

Source Mask Optimization (SMO), dating from the mid-2000s, is another important application of computational lithography concepts in optical lithography as it is practiced today.

”It is fair to say that current optical lithography capabilities would be impossible without the use of computational lithography tools, and these techniques will only become more essential in the future,” says Dr. Mack.

[N.B. Multiple Patterning (MP) technology is also needed for the current generation of semiconductor device designs. Double patterning technology (DPT) is required for the 22 / 14nm technology node, and triple patterning or quadruple patterning (QP) for 14 / 10nm.]

The figure below illustrates a simplified flow of how computational lithography is used today. As shown: the sequence of photomask data processing, from design to chrome, and then of wafer processing, from chrome to wafer, consists of computational lithography modules including MP (Multi-Patterning), SMO (Source Mask Optimization), OPC (Optical Proximity Correction), SRAF (Sub-Resolution Assist Feature), MRC (Mask Rule Check), Verification, and MDP (Mask Data Processing).

computational lithographySource:  Brion Technologies

The first step in this flow is to decide the scanner source (or illumination), which significantly impacts CD accuracy, based on critical clips of the chip layout data. A source mask optimization tool is essential for advanced scaling. Once the source is determined, mask optimization of the full-chip layout is carried out using the optimized source. The flow of this process is:

1)    A pre-OPC step is used to bias patterns with a known strong etch process influence,

2)    The SRAF size and placement is determined,

3)    The mask pattern undergoes OPC,

4)    A final full-chip process window verification check is performed to see if any lithographic hot spots are found, with a feedback loop if this is the case.

Only after all the optimized design data passes the verification process is the data sent to data fracturing for the mask making process.

The graphic below, published by imec, shows a practical example of using computational lithography on a 22nm design contact layer. Without an optimized source and mask (“Standard illumination” in the figure) the process window is essentially too small for manufacturing, even with double patterning.

computational lithography on a 22nm design contact layer

Source:  Brion Technologies; imec

Overall, computational lithography has been, and continues to be, a key enabler to achieving the very fine printed image resolutions needed for the process node shrinks that keep the semiconductor industry progressing on its Moore’s law roadmap even as the industry awaits EUV, or another next-generation lithography technology, to be introduced into High Volume Manufacturing.

Bringing awareness of different aspects of semiconductor manufacturing challenges is a primary role of SEMI. One of SEMI’s key technology conferences, the Advanced Semiconductor Manufacturing Conference (ASMC), is now in its 24th year, and will be held once again at the Saratoga Hilton Hotel, from May 13–16 2013, in beautiful Saratoga Springs, New York. The computational lithography theme runs strongly throughout ASMC 2013, starting with the first paper in ASMC 2013 Session 1, covering work in computational lithography presented by GLOBALFOUNDRIES, and continuing through into a special tutorial on computational lithography led by Intel Fellow Dr. Vivek Singh, Technology and Manufacturing Group director, Computational Lithography.  

Additional ASMC 2013 keynotes and tutorials from recognized industry leaders include talks by Subramani Kengeri, vice president, Advanced Technology Architecture, Office of the CTO, GLOBALFOUNDRIES; Tim Hendry, vice president, Technology and Manufacturing Group, Intel; and Bill McClean, president, IC Insights.  

ASMC 2013 will also feature a 3D-IC tutorial by Sarasvathi Thangaraju, MTS at GLOBALFOUNDRIES, and a 450mm panel discussion led by Paul Farrar, general manager of Albany, New York-based G450C, with executives from Applied Materials, KLA-Tencor, Soitec and TSMC weighing in on where, when, and how much it will cost for the conversion to 450mm wafers from the industry’s current 300mm wafer standard.

For more information, please visit www.semi.org/asmc2013 or contact Margaret Kindling at mkindling@semi.org.


Paul Werbaneth is a Steering Committee member, SEMI Advanced Semiconductor Manufacturing Conference. 

April 9, 2013