Speeding 3D-IC to Commercialization: Update on SEMI Standards

Speeding 3D-IC to Commercialization: Update on SEMI Standards

By James Amano, SEMI International Standards

Republished with permission from Chip Scale Review (March/April 2013)

The industry is poised to jump from concept to commercialization with 3-D technologies. Given their potential for increased performance, smaller footprint, and reduced cost and power consumption, 3D-IC technologies are now on the leading edge of innovation. 3D integration using through-silicon vias (TSVs) promise a fundamental shift for current multi-chip integration and packaging approaches. But cost- effective, high-volume manufacturing will be difficult to achieve without standardized equipment, materials, and processes, especially because 3D-ICs' design and mechanical complexity can lead to increased manufacturing defects, as well as thermal management issues and signal interference.

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Multiple manufacturing challenges must be resolved to move forward. Focusing on 3D-IC technology and the manufacturing process will help reduce costs through increased throughput, improved product quality, better yields, and lower maintenance and operational expenses. No single company can fully realize these benefits without working closely with their suppliers and their competitors. Highly-automated and advanced manufacturing systems comprise multiple equipment types, technologies and supporting products from best-in-class suppliers from around the world. Enabling these different processes, products and technologies to work seamlessly and cost-effectively together requires diverse, well-informed and effective industry standards.

Understanding the essential role of standards in enabling low-cost, high-quality manufacturing, SEMI first charged its International Standards group with exploring the challenges of 3D-IC manufacturing issues in spring 2010. The first 3DS-IC (where the “S” stands for “stacked”) SEMI Standards Technical Committee was formed in North America in late 2010, with a counterpart in Taiwan created in July 2011. In early fall 2012, the Japan Packaging Committee authorized the formation of a 3D-IC Study Group with plans to explore and ultimately engage in the activities in North America and Taiwan (Figure 1).

TSV Geometrical Metrology

The 3Ds-IC SEMI Standards committee’s first accomplishment was SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology. SEMI 3D1 provided a starting point for standardization of geometrical metrology for selected dimensions of through-silicon vias (TSVs).  Although different technologies measured various geometrical parameters of an individual TSV, or of an array of TSVs — such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter — it was difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry. The Inspection & Metrology Task Force recognized the need for such a standard. SEMI 3D1 is an important first step in promoting common understanding and precise communication between stakeholders in the 3D-IC manufacturing supply chain.

Organization Charts

Figure 1: SEMI International Standards organization chart 

Glass Carrier Wafer Specs

Recently at the North America (NA) Standards Fall 2012 meetings, the NA 3DS-IC Committee approved SEMI Draft Document 5482, New Standard: Specification for Glass Carrier Wafers for 3DS-IC Applications. Developed by the Bonded Wafer Stacks Task Force, this specification addresses the needs of the industry by providing the tools needed to procure pristine glass carrier wafers for use in 3DS-IC processes.

SEMI Draft Document 5482 describes dimensional, thermal, and wafer preparation characteristics for the glass starting material that will be used as carrier wafers in a temporary bonded state. This specification also describes glass carrier wafers with nominal diameters of 200 and 300mm, and a thickness of 700nm, although the wafer diameter and thickness required may vary due to process and functional variation. Such variations need clarification in the purchasing order or in the contract. Methods of measurements suitable for determining the characteristics in the specifications are also indicated (Figure 2). Document 5482 is on track to be published as SEMI 3D2 in early 2013.

SEMI 3DS-IC Standardization Activities Continue

The NA Three-dimensional Stacked Integrated Circuits (3DS-IC) Committee and its associated task forces met in conjunction with the NA Standards Fall 2012 meetings in San Jose, California in July. Summaries of task force activities are presented below:

Bonded Wafer Stacks Task Force. In addition to the development of SEMI Draft Document 5482, the Bonded Wafer Stacks Task Force will continue development of SEMI Draft Document 5173B, New Standard:  Guide for Describing Materials Properties and Test Methods for a 300mm 3DS-IC Wafer Stack, which failed technical committee review based on inputs received from the Cycle 6 voting period. The task force plans to reballot this document as 5173C for the Cycle 1, 2013 voting period. The task force will also continue to work on the SEMI New Activity Report Form (SNARF #5174, New Standard: Specification for Identification and Marking for Bonded Wafer Stacks).

Inspection & Metrology Task Force. The Inspection & Metrology Task Force received committee approval to develop a new test method for measuring warp bow, and TTV on silicon and glass wafers as SNARF #5506.

Current metrology strategies have evolved from methods used to characterize smaller, lower aspect ratio geometries. Conventionally, three-point mounts have been used to measure flatness/warp of wafers along with the gravity compensation. For instance, 3DS- IC applications use larger and thinner wafers than conventional applications. Large, thin wafers have inherently low stiffness, leading to large deflections, which make compensation more challenging. Ball mounts cause large deflections, four-point and ring supports have redundant support and are sensitive to how parts are placed on the mount.


Figure 2: Optional A/N code field location on back surface of 200mm and 300mm diameter glass wafer Source: SEMI 

The industry benefits from identifying an alternate test method that better reflects the application usage of these wafers. One approach used in the industry is a similar set up to Sori with a wire mount and a non-contact scanning method that allows depicting a complete picture of the wafer’s shape and dimensional parameters.

SNARF #5506 will lead to the development of a new test method that accurately and reliably depicts the dimensional shape of single silicon and glass wafers that are ≥300mm in diameter and ≤775µm in thickness and that uses a wire mount and laser scanning interferometry. This method will recommend that the wafer is characterized in a position that allows for a free state profile measurement on a flat surface. The document will include applicable ranges for valid measurements where possible.

The Inspection & Metrology Task Force will also continue its work on the following standardization activities:

  • New  Standard:  Guide  for Measuring Voids in Bonded Wafer Stacks (SNARF #5270)
  • New  Standard:  Guide  for Metrology Techniques to be used in Measurement of Geometrical Parameters  of  Through- Silicon Vias (TSVs) in 3DS-IC Structures (SNARF #5410)
  • New Standard: Terminology for Measured Geometrical Parameters of Through- Glass Vias (TGVs) in 3DS-IC Structures (SNARF #5447)

SEMI Draft Document 5410 is scheduled to be submitted for the Cycle 1, 2013 voting period, which occurs January 3-February 15.

Thin Wafer Handling Task Force. The Thin Wafer Handling Task Force is nearing completion in its development of SEMI Draft Document 5175, New Standard: Guide for Multi-Wafer Transport and Storage Containers for 300mm, Thin Silicon Wafers on Tape Frames. Ballot 5175 is scheduled to be submitted for the Cycle 1 2013 voting period.

Taiwan 3DS-IC Activities

The Middle End Process Task Force formalized its standardization efforts via SNARF #5473 (New Standard: Guide for Alignment Mark for 3DS- IC Process) and SNARF #5474 (New Standard: Guide for CMP and Micro- bump Processes for Frontside TSV Integration). The task force plans to submit SEMI Draft Document 5474 for balloting in early 2013. The Testing Task Force also received approval to begin work on a new guide for Incoming/Outgoing Quality Control and Testing Flow for 3DS-IC Products as SNARF #5485. [For more information about Taiwan 3DS-IC activities, please contact Ms. Catherine Chang (cchang@semi.org) at SEMI.]

Ballots for the above activities will be issued throughout 2013, and are just the beginning of this global, industry-wide effort. Over 160 technologists from industry, research institutes, and academia around the world have already joined the SEMI 3DS-IC Standards Committee and are at work on these critical standards.

Pre-competitive collaboration is  difficult, and involves hard work by industry experts, but it creates significant benefits for the industry as a whole, for companies participating, and for individuals involved in the process. If you or your company is not yet involved in these efforts to shape the future of 3D-IC, learn more about SEMI Standards by visiting www.semi.org/en/Standards. Note that participation in the SEMI Standards Program is free, but requires registration. To learn more, contact jamano@semi.org or register at: www.semi.org/standardsmembership.

Attend SEMICON West 2013 Standards meetings: www.semi.org/node/45276

This article was originally published in Chip Scale Review (March/April 2013 issue). Reused with permission.

April 9, 2013