Heterogeneous Packaging Technology Eases Integrated Photonics
Heterogeneous Packaging Technology Eases Integrated Photonics
By Paula Doe, SEMI Emerging Markets
Suppliers now see emerging heterogeneous packaging solutions for integrating photonics with electronics as a practical path forward to bring optical speeds to the semiconductor industry.
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Photonics systems on silicon may be starting to move from the active optical cable to the circuit board for high-speed data communication. Leading companies like Cisco, STMicroelectronics and Luxtera are investing in the infrastructure for what they see as a widely applicable platform, enabled by developments in advanced packaging technology for heterogeneous integration of the optics with electronics on silicon interposers or with ultrafine copper pillar bumping.
Silicon photonics is still a tiny incipient market. Yole Développement figures total sales of these products using active and integrated passive elements on silicon, including transceivers and active optical cables, came to about $65 million last year, and will likely climb to some $215 million by 2017. Some 80 percent of that total is for data communications applications, the vast majority of it shipped by the two main commercial suppliers Luxtera and Kotura. Yole includes as silicon photonics devices with active elements that generate, detect or actively change light signals, integrated with passive elements like wave guides or filters, built in any size geometry on SOI wafers. They typically include very few transistors –usually just current and voltage drivers, not complex digital logic.
Source: Yole Développement, Silicon Photonics, 2012
Suppliers See Growing Demand to Move Optical Conversion Close to the Chips
But market demand for higher speed data communication is growing fast, and making the modulators, multiplexers, wave guides and detectors all in CMOS brings down costs and improves speeds dramatically from the traditional assembly of separate optical components. “The optical world does assembly in Asia Pacific with tweezers, and we’ve gotten to the point where that no longer works,” says Kotura VP of marketing Arlon Martin. “We need the low cost integration of making it all in silicon, and the low cost packaging of the electronics world.”
A picture of a 100 Gb/s silicon chip measuring roughly 3 x 8 mm. The chip has integrated germanium detectors to convert four WDM optical signals to electrical. Source: Kotura
An abstract view of a WDM demultiplexer. One input channel with many parallel channels on different wavelengths of light is separated by an Echelle grating before conversion to electrical. Source: Kotura
The driving application will be mid range, 300m to 2km data transmission, at 25Gbps and above, as at those speeds signals from the alternative low cost VCSEL technology degrade at distance. And once users start converting computer electrons to photons, the sooner in the system the conversion, the better the gains. The first step was active optical cables between server units and pluggable transceivers at the front panel, but the sector is looking next at putting optical transceivers on-board next to the high speed ASICs for super computers. Systems making the conversion at mid board are now being designed for introduction in 2015-2016, says Martin.
“ASICs are becoming so powerful at 28nm and beyond that the multi-terabyte density of data is too much for traditional optics to bring out at the front plate without thermal and signal integrity issues,” explains Chris Bergey, Luxtera VP of marketing. “So the current focus is to put the optical engines close to the switch chip or ASIC, for short traces close to the silicon that decrease power, complexity and cost. With the data center’s interest in moving to single mode optical fiber for greater reach, future scalability and lower cost, proponents argue that the size, cost and power advantages of silicon devices will likely propel the technology into more of the market.
“Once we have a robust and proven technology it will be used across optical networking applications,” says Pietro Maestri, marketing director for STMicroelectronics’ Mixed Process Division. “It will be a strong opportunity for standardizing the optical interfaces at all levels.”
Big Players Step Up Investment for Wider Applications
“Silicon photonics is a key technology for us,” says Bill Swift, Cisco Systems VP of engineering, now leading the company’s transceiver module business. “It’s one of the technology bets we have to make to decrease size, cost and power of high-speed optical interfaces. It will be key for 40G and 100G interfaces, and we will scale it across all our products.” He reports the company sees no showstoppers in moving rapidly ahead with the CMOS-based photonics technology acquired with LightWire for some $270 million earlier this year. Swift stresses the key role of recent advanced packaging developments in 2.5D and 3D heterogeneous integration for packaging and assembling the silicon photonics with lasers and high-speed CMOS devices. “The intersection of the silicon and optical world is pretty exciting right now,” he notes.
STMicroelectronics is another leading electronics player investing, aiming to offer silicon photonics foundry services, starting with volume production for industry leader Luxtera in 2014. ST also aims to develop a platform technology and the necessary ecosystem to produce its own products for its customers as well. “After some years of investigation we decided it was time,” says Maestri. “The turning point was that, on the one hand, the technology is maturing, and, on the other hand, we’re seeing growing interest. We intend to serve this market in the fastest and most determined way, as the first step in a long story.”
Industry pioneer Luxtera is now focusing on building out the infrastructure to enable volume manufacturing. It has supplied its process to partners STMicroelectronics and OpSIS for open foundry use, and is working with equipment and packaging suppliers as well to try to create silicon-industry-like production efficiency. “It’s selfish — we need this to scale our supply chain, and it’s a way to monetize our IP. We need to scale to support the opportunities of large OEM flagship products, and once the tools are available it can go very quickly,” says Bergey.
Luxtera plans to provide a second source for its own production at ST’s 300mm Crolles fab, allowing it to take advantage of the latest tools and higher throughputs, and reports it plans to bring up another fab or two in the next few years. It’s working with a major OSAT to offer optical attach and optical connectors with scalable volume processes. Luxtera is also working with Tokyo Electron to enable optical probe testing and characterization of the photonics chips. After developing the needed volume technologies with one key partner, Luxtera expects that partner to sell to other users as well, while Luxtera plans to roll the technologies out to more suppliers to create a more robust supply chain. “There’s a whole ecosystem that has to be built out as systems move from copper to optical interfaces for 25Gbps and beyond — it’s a big transition,” says Bergey.
One big step is the improved availability of multi-project photonics wafer shuttles to bring down development costs through the OpSIS foundry services, using fabs at Luxtera in the U.S. and IME in Singapore. The effort has been largely funded by the U.S. Air Force, DARPA and Intel, with much in-kind support from the supply chain, including design software suppliers Mentor Graphics, Lumerical and Synopsys. University of Delaware professor Michael Hochberg, director of the project, reports OpSIS supplies complete designs and PDKs for optical modulators, wave guides and photo detectors for 25Gbps devices. “These are close to commercial quality devices,” he says. “And a bunch of commercial users are in development phase.” Hochberg notes that as the developing infrastructure brings costs down, a much wider range of applications for silicon photonics become interesting, including things like disposable biosensing devices for medical diagnostics, down-hole sensing for the oil and gas industry, test and measurement applications, chip-to-memory connections, and assorted ways for photonics to take over some of the job of the radio front end to push more bits through the channel. “That list doesn’t include the things our foundry users are putting on their photonics chips, many of which are quite surprising,” Hochberg adds.
Hetereogenous Integration May Accelerate Development
Integration of silicon photonics could be accelerated by the datacomm sector’s move to heterogeneous integration of its ASICs on interposers. “When the high-power, reticule-busting datacomm ASICs need to go to heterogeneous integration on silicon interposers, they can put the photonics on the interposers too,” proposes Bergey. The photonics, with no active transistors at all, could be made on the interposer before the vias, with attachment to the optical fiber made with an optical block (optical bond pads of graded couplings) on top of the overhang on one side of the interposer. These optic connections direct to the upstairs die could bring the signal in and out of the ASIC optically, potentially significantly reducing system power and costs. Bergey suggests this interposer approach could be as close as a few years out for high performance computing and data center servers, moving as well to connect memory stacks and CPU logic, as 2.5D becomes a volume process. “We’ve even had cell phone suppliers come to us wanting to increase memory bandwidth while separating the memory from the processor to reduce the heat, but that’s a ways out,” he notes. Like other suppliers currently focused on commercial manufacturing, Bergey argues that attempting to also create the laser on the silicon doesn’t make a lot of sense, as separate lasers provide more flexibility for choosing the most optically efficient source for many applications. “Our light source is just an optical power source, like a DC power supply,” he adds. “It can be placed on the chip, somewhere else on the board, or even hundreds of meters away for many applications.”
ST’s silicon photonics products will put the optics and the electronics on separate die, stacked together with ultra fine copper pillar bumps. Integration of the optical components and the complex BiCMOS electronics in a monolithic process, with their incremental masks, would be quite expensive, says Maestri, with the higher wafer cost and lower yields on large die with high mask count. Instead, ST is developing with its partners a new, fine-pitch copper pillar technology to fuse the two die. It’s also working on developing design tools able to simulate optical as well as electrical inputs and outputs. For easier industry acceptance of the new technologies, the company’s strategy is to start with relatively simple photonics devices, then to move step-by-step into integration of progressively more complex systems as customers get more used to trusting these technologies. Integration of the lasers on silicon looks particularly far in the future. “It’s still an R&D project, perhaps 5 to 10 years away from production,” Maestri argues. “Silicon and InP are two quite different materials. It’s one thing to demonstrate integration, and quite another thing to manufacture it in volume. The integrated laser will need years of real testing — not simple laboratory accelerated testing — before it is accepted by the industry.”
“For best optical and electrical performance, integration will be heterogeneous. Integration on a 2.5D interposer or with front-to-front copper pillar bonding is good enough,” concurs Hochberg, noting that monolithic integration with truly advanced electronics nodes is a bad idea for both technical and economic reasons. The electronics and photonics processes become even less compatible at more advanced CMOS nodes. Adding photonics to the back end of the process adds layers to expensive wafers that will reduce yield and performance. Adding photonics to the front end of the line steps means wasting expensive transistor wafer area for structures that don’t need precision. But some applications will opt to trade off some performance for the added robustness or simpler supply chain of monolithic integration. Eventually being able to integrate the laser directly on the chip will provide enormous advantages for some applications, so DARPA may use SoC while data centers use SiP solutions. “If 3D packaging technology had existed earlier, companies may not have pursued monolithic integration,” he notes. “The 3D packaging technology will be hugely impactful in this space.”
The trend is for separate processes and heterogeneous integration, concurs Kotura’s Martin. He notes that earlier work focused on integrating lots of transistors with the optics on the same chip, but most recent work now focuses on separate chips. “The industry has moved away from full integration because packaging now works great,” he notes.
Supplier Opportunities in Silicon Photonics Ecosystem
But there are plenty more challenges to overcome for silicon photonics to become mainstream. Hochberg notes that silicon is actually cheap and high yielding only in high volumes, and with the good data and statistical process control of long established silicon processes. Photonics still has work to do across the board to get to those levels, and the initial data center market alone is very small.
The fab technology for photonics on silicon is relatively standard CMOS, with SOI wafers, DRIE for etching MEMS-like dimensional features, and high-speed analog-like processes. Features are relatively large, at 130nm or .25µm, but the line-edge roughness and overlay specifications require more advanced lithography, typically at least 65nm. “193 dry lithography is in use now, and 193 wet will be used in the near future,” says Hochberg. Unlike semiconductors, however, photonics needs masks and software to handle curved structures. “There’s nothing in the conventional semiconductor ecosystem that is specified to deal with extreme non-Manhattan structures,” he notes.
Most challenges and opportunities are in packaging and test. Surface mounting can remain a challenge. Hochberg lists the need for test structures, design for test and parametric extraction, and measurement methodology, especially for second and third order effects, for the optical and electrical properties and the interactions between the two. The sector also needs methods and standards for in-fab and out-of-fab qualification for the photonics, and automated wafer-scale test systems for both electrical and optical test, at challenging test speeds up to >70GHz. OpSIS currently is customizing equipment and developing its own algorithms, leaning heavily on equipment donated by Tektronix.
Hochberg argues that there are multiple workable solutions for fiber-to-chip attachment, but significantly more investment will be needed to get to really high volume, low-cost production, and many companies will probably define their competitive advantage by their particular solution. While the electronic industry’s pick and place machines have the precision required for optical alignment, the volume packaging infrastructure does not yet exist.
ST is working with its suppliers to develop equipment to measure and characterize its diffusion process, aiming for a consistent path from R&D to volume production tools. Now that its fab process is more established, the company is also starting to work on the complex issues of alignment and testing of the connection of the optical fibers and lasers to the chip, where it intends to work with assembly companies and customers to help speed development of enabling solutions. “There is a lot of work still to do in packaging solutions,” concurs Maestri.
While silicon photonics makers all aim to use mainstream CMOS processes, there are distinct differences in technology among the early suppliers. Kotura, for instance, uses much larger waveguide channels than Luxtera, on the order of microns instead of sub-microns, which it says reduce losses in transmission and simplify wavelength multiplexing and demultiplexing, and it extracts light out the edges of the chip instead of out the top, allowing more planar integration.
“Many approaches will be successful — there isn’t going to be one winning technology,” notes Hochberg. “But the most successful will be those approaches that freeze the process and develop a large design community. Having a community of users who develop a diverse set of products in a single technology spreads the risk and cost.”
Research Pogress on Bonding III-V Laser Materials to Silicon before Processing
Others are looking at heterogenous integration of III-V materials at the wafer level before processing, so the laser can be made in the same CMOS process flow as the rest of the photonics on silicon. Intel researchers demonstrated a research prototype for 50Gbps data communication some time ago, made by bonding InP to the silicon and then making the laser along with the rest of the photonics elements. Since then CEA-Leti and the Alcatel-Lucent Bell Labs joint venture III-V Lab have demonstrated a tunable laser made on InP bonded to silicon. The California startup Aurrion is working on commercializing a similar approach, bonding chiplets of III-V optical materials to the silicon wafer, either die-to-wafer, or small III-V wafers to large Si wafer, then thinning the stack down to the thickness of a few microns before processing the wafer in a CMOS foundry. This integration before processing allows use of different materials for best performance, but wafer-level processing for best cost and fewer coupling losses, suggests Eric Hall, Aurrion VP of marketing and business development. The photonics materials could potentially be added on top of CMOS circuitry. “The challenge is extending traditional process tools to non-traditional materials,” says Hall. “We need to work closely with our foundry partners to get traditional electronic foundry processes to yield photonic devices.”
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