Background on 450 mm Wafer Transition
Sept 1, 2012
The industry transition to 450mm wafers for leading-edge chip manufacturing will be one of the most complex and costly decisions in the history of semiconductors. Previous wafer size increases have occurred with significant industry wide investment, particularly the move to 300mm wafers about ten years ago, which required billions in research and development. The 300mm transition, combined with other simultaneous productivity improvements, produced huge economic advantages for many chip makers on a cost-per-die basis. Some would argue that it also led to a severe consolidation in the industry and negative financial returns to the supply chain. Every wafer transition requires enormous R&D investment by manufacturers and suppliers, and close collaboration among all sectors of supply chain to ensure a unified, coordinated transition. This will be especially true for the move to 450mm, which will coincide with many other device scaling and materials integration challenges.—This article provides a summary on the background, status, and challenges for a successful transition to 450mm wafers for advanced chip manufacturing.
The Cost Reduction Imperative
Reducing the cost of semiconductors has been one of the most powerful economic and social forces of our time. It has driven the Information Age and defined our modern life. Innovations in the semiconductors have not only impacted computers and information technology, but entertainment, health care, energy, communications, and more. They are helping modern economies grow and helping create a productive middle class in emerging markets around the world.
To understand the scale of semiconductor cost reduction, since 1975 the cost of one transistor has been reduced by a factor of about 4 million. To put this into perspective, if you use the average cost of a transistor in 1976, the cost of a simple iPod music player would cost about one billion dollars. It also would be the size of a building. To take another example, smart phone users today have as much computing power in the palm of their hand as was used in the Apollo spacecraft that went to the moon.
Most of this cost reduction has been due to photolithography-based scaling that enables the pitch and feature size of a transistor to be continuously reduced. Moore’s Law, the prediction that the number of transistors that can be placed inexpensively on an integrated circuit would double approximately every two years, is primarily based on scaling. But feature-size reductions accounted for only about 8000X of the 4 million times reduction in chip cost since 1975 as chip geometry went from about 4 microns to 45 nanometers. The remaining 500X cost reductions have been due manufacturing efficiencies that improve yield, increase throughput, reduce cost, raise equipment productivity, and wafer size increases that occur about once every 8-10 years.
The Impact of Larger Wafers
In 2005, some chip manufacturers believed that the industry was facing a significant shortfall from the productivity improvements predicted by Moore’s Law. They believed the traditional rate of reduction in the cost per transistor could not be maintained without an increase in wafer size to 450mm wafers. Increases in wafer area can increase the number of dies per wafer and lead to a theoretical reduction in die cost of approximately 30 percent (if all other costs remain constant). The semiconductor industry has increased wafer size about once every 10 years. The industry first started using 200 mm wafers in 1991 and then switched to 300 mm wafers in 2001. Once a new wafer size has been implemented in high volume manufacturing, advanced development of equipment for smaller size wafers has stopped as manufacturers concentrate their R&D resources on the next generation wafer fabs.
It has been estimated that the cost of the 300 mm wafer transition was $12 billion, with the investment spread over the 1996 to 2003 timeframe. Much of this investment was made by equipment suppliers, many of whom believe they have yet to recoup their investment in the 300mm transition. Cost for the transition to 450mm has been estimated to range from $8 to $40 billion. Critical to the successful transition to 450mm is proper timing of the move to coincide with lithography node, something that didn’t happen during the 300mm transition. Equipment suppliers cannot profitably support both 300mm and 450mm equipment designs at the same advanced node.
Equipment suppliers and chip manufacturers have had different perspectives on the 450mm wafer transition. These perspectives were summarized in 2011 by Bob Johnson, Research VP at Gardner, “When you look at it from the perspective of the semiconductor manufacturer, it’s really quite simple, cheaper equipment and production costs for the same incremental output. They save money…primarily in capital equipment. When you look at it from the equipment manufacturer side, you’ve got a really good question. We’ve got the opportunity to spend billions of dollars on R&D that could go for other projects and end up cutting our market by about 30% going forward.” He said, “450mm creates a fundamental conflict of interest between the semiconductor and equipment manufacturers and this conflict of interest has to be resolved if we’re going to go forward.”
450mm a Go
In September 2011, the State of New York committed state funding to leverage industry contributions for establishment of the Global 450 Consortium (G450C) at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. The unprecedented consortium is comprised of five leading international companies: IBM, Intel, GlobalFoundries, Samsung and TSMC. The purpose of G450C is to develop a pilot line to demonstrate 450mm wafer tools and process capabilities. The pilot line will consist of approximately 50 different tool types for making the industry’s most advanced semiconductors, with at least two suppliers for each different tool. Results and data of the pilot line will be used to qualify vendors and further develop process equipment for high-volume manufacturing.
Industry consortia (ISMI, SEMATECH) have supported 450 mm wafer development and material handling requirements through a number of programs and demonstration projects. They have evaluated most of the necessary material handling solutions including personal guided vehicles (PGVs) and will demonstrate automated materials handling system (AMHS) components including new 450 mm stockers and overhead hoist transport systems. They have created a “wafer bank” to lend test wafers to equipment developers and provided prototype testing of 450 mm factory integration equipment, including lab testing focused on 12 mm pitch FOUPs, MACs and load ports.
SEMI International Standards development has also advanced pilot deployment and provided a platform for future development work. SEMI published its first 450 mm wafer standard in 2008 – SEMI M76, Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers – and has published 15 more including specifications for carriers, load ports, interfaces, and other areas. The SEMI Standards Program currently has 11 task forces working on 450 mm-related activities with 11 draft standards in the pipeline.
While industry readiness has accelerated with industry standards, test wafer availability, and materials handling infrastructure, much of the critical process technology development has not yet begun. Critical development work on key deposition, etch and other processes is in the early phases.
Funding the Future?
Considerable questions remain on how the industry will fund the costly development of 450mm chip manufacturing. An industry-wide mechanism for transparent R&D cost and risk sharing and timely tool development has not been announced and may never materialize. Chip manufacturers and G450C are conducting concurrent negotiations with suppliers on equipment roadmaps, terms, non-recurring engineering (NRE) costs, and other factors.
In July, the world’s largest chip maker, Intel, announced plans to make a $4.1 billion investment in ASML, the leading lithography equipment supplier, partly to ensure 450 readiness. In August, TSMC, the world’s largest foundry, also announced an investment in ASML to “speed up the deployment of new technologies for 450-millimeter wafers.” It is uncertain if direct investment in other suppliers or other direct R&D funding mechanisms will be developed by chip makers and consortia. Chip makers and industry consortia are currently negotiating on a case-by-case basis with leading suppliers of every key tool set. While much is still not known about scope, scale and strategy of this direct funding approach, it is a departure from traditional consortia funding and roadmap development models.
The large role that subsystem and component suppliers play in semiconductor manufacturing further complicates the funding requirement. . ASML reports that 90% of the company’s lithography system components and subsystems are provided by outside suppliers. Applied Materials is dependent on 800 suppliers worldwide, with 75 prime strategic suppliers representing 80 percent of their annual procurement allocation. How these suppliers are compensated for advanced 450mm development is also subject to individual negotiations.
While R&D funding issues present tough negotiations for chip manufacturers, OEMs and suppliers, the transition to 450mm opens up strategic opportunities for many companies. Both chip manufacturers and companies throughout the supply chain are exploring ways to gain long-term competitive advantage through the wafer size transition. Suppliers of critical equipment or subsystems will see an opportunity to gain share or margin through 450mm investments. Foundries will see 450mm as a way to further compete with and for IDM business; and 300mm fabs will be used for products being made today on 200mm fabs. The dynamics set in motion through the introduction of 450mm fabs will be felt throughout the industry.
The semiconductor industry has achieved many of the most complex technical developments in modern science. The industry has also been able to overcome many of the production and manufacturing barriers to sustain Moore’s Law for over 40 years and bring the marvels of modern electronics to billions of people worldwide. How the industry meets the business model and industry-collaboration requirements for a successful 450mm wafer transition has yet to be demonstrated, but if it does, it will be on an accomplishment on a par with anything that has been achieved in a semiconductor lab or fab.
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