As Memory Moves Ahead
As Memory Moves Ahead
Future of Memory: “Universal Memory” not likely, but today’s R&D discoveries point to possible Memory technology successors
By Er-Wuan Ping, managing director, Silicon Systems Group, Applied Materials
Satisfying evolving functionality and form factor demands of burgeoning consumer mobile technologies is giving rise to complex challenges in designing and fabricating the integrated circuits that enable them. These challenges include demands for memory that performs faster, has larger capacity, and uses less power. Volatile DRAM and non-volatile Flash memory devices have scaled two-dimensionally over multiple technology nodes in pursuit of faster performance and lower cost. Flash in particular has proliferated throughout consumer and commercial electronics, such as cell phones, digital cameras, solid-state devices, wireless communications, and medical products.
But these technologies are encountering scaling limits beyond the 2x nm node as reliability, power consumption, and structural complexities that limit yield and increase cost become more significant. Power consumption is one of the top issues affecting mobile and data center applications while memory performance is becoming the key bottleneck limiting system performance as applications become more data-centric and less computational.
It appears that the most likely immediate successor to planar NAND will be 3D NAND although this new approach still faces complex process challenges, such as creating high-mobility silicon channels, and the deposition and etch of extremely high-aspect-ratio features (potentially >80:1). If these are overcome in the next few years, NAND scaling will continue in terms of density and cost, making it more difficult for ReRAM to compete with 3D NAND on the basis of cost. Nevertheless, ReRAM with its scalability, speed, low-power operation, endurance, and compatibility with established CMOS fabrication processes may yet become the technology of choice in parts of the memory market at 1x nm and beyond.
ReRAM is attractive for several reasons. The first is speed. Several studies have demonstrated switching speeds of a few nanoseconds, i.e., three to four orders of magnitude faster than NAND.[1,2] The second benefit is low operation voltage, which is about 1V (except for the forming process) or 20 times lower than NAND. The third reason is ReRAM’s better endurance compared to NAND, whose endurance degrades as device size decreases. For these reasons, research continues on integrating ReRAM in single-stack embedded memory and stand-alone stacked memory configurations.[3,4]
As a practical matter for bringing ReRAM technology to production, however, much materials and interface characterization remains to be done to arrive at an optimized materials system for the ReRAM cell and the most effective array structure for achieving the low-power operation desired for mobile devices. Fortunately, once these issues have been resolved, ReRAM fabrication will be feasible using established CMOS technologies, such as ALD, CVD, and RFPVD.
As for DRAM and SRAM, many consider magneto-resistive RAM (MRAM) to be the technology that most closely matches their performance — with the added benefit of non-volatility. Manufacturability and scaling issues have limited its commercialization to date, although researchers around the world are making notable progress in improving MRAM’s implementation prospects.
Among MRAM technologies spin-transfer torque or STT-MRAM appears to have fewer limitations than the others. It offers non-volatility, extended scalability, excellent endurance (exceeding 1015 cycles) at lower power, and fast “read and write” speeds. It is also much smaller than current SRAM.[5-8] But STT-MRAM fabrication poses broad challenges from material complexity of the structure to process integration issues. Many ultra-thin layers with widely varying characteristics are present in the device. Interface engineering will be crucial to successfully combining these materials.
Magnetic film characteristics pose further challenges. They are susceptible to corrosion, so effective passivation is of great importance to protect them from penetration or diffusion of process chemicals, such as oxygen, chlorine, and bromine, which can alter the structure and properties of the films to reduce the magneto-resistive effect. The magnetic moments of these films depend strongly on their grain and grain boundaries, as these factors affect programming current. In addition, magnetic switching between the fixed layer and the free layer through the tunneling oxide separating them is greatly reduced by the boundaries of the grains. Signal-to-noise ratio also degrades as grain boundary increases or the number of grains in a given area decreases below a certain threshold. As STT-MRAM cell size scales down, noise levels or signal inconsistency across the array increases, with these variations becoming relatively larger.
As regards integration, the relatively low-temperature STT-MRAM processes (typically <350°C) have the advantage over other embedded memory technologies of compatibility with back-end-of-line thermal budgets. Nevertheless, the total thermal budget allocated to post-magnetic tunnel junction processing should be carefully controlled to protect against adverse effects. For example, subsequent high-temperature processing can cause thermal fluctuation of magnetization, while physically stressing the wafer can also alter magnetic properties based on changes in grain boundaries and interface properties.
Broader implementation challenges involve achieving low current density and high reliability in array operation. Besides increasing power consumption for large arrays, high current density increases electrical stress and shortens transistor lifetime. Another consideration will be provision of magnetic shielding during assembly and testing to protect pre-magnified cells from external magnetic fields.
Optimists may hope for a “universal memory” to emerge from next-generation research and development. While such an outcome is probably not likely, the semiconductor industry will undoubtedly benefit from numerous discoveries made in pursuing optimal successors to today’s memory technologies.
 B.Govoreanu, et al., “10x10nm2 Hf/HfOx Crossbar Resistive RAM with Excellent Performance, Reliability and Low-Energy Operation,” IEDM, p. 729, 2011.
 C. Hermes, et al., “Analysis of Transient Currents During Ultrafast Switching of TiO Nanocrossbar Devices,” LED, pp.1116-1118, Aug. 2011.
 I.G. Baek, et al., “Highly Scalable Non-Volatile Resistive Memory Using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses,” IEDM, p. 587, 2004.
 H.S.Yoon, et al., “Vertical Cross-Point Resistance Change Memory for Ultra-High Density Non-Volatile Memory Applications,” VLSI, 2009.
 Farhad Tabrizi, “The future of scalable STT-RAM as a universal embedded memory,” http://www.eetimes.com/design/embedded/026000/The-future-of-scalable-SST-RAM-as-a-universal-embedded-memory, retrieved October 7, 2011.
 Dong, X., et al., “Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement,” Proceedings of the 45th annual Design Automation Conference, Anaheim, California, June 2008.
 Dong, X., et al., “Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems,” Proceedings of the Conference on High Performance and Analysis, Portland, Oregon, November 2009.
 C.J. Lin, et al., “45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T/1MTJ Cell,” International Electron Devices Meeting, IEEE International, pp.279-282, Dec. 2009.
 Chang Soo Kim et al., “Thickness and temperature effects on magnetic properties and roughness of L10-ordered FePt films,” IEEE Transactions on Magnetics, Vol. 46, No. 6, pp. 2282-2285, 2010.
 Kangho Lee and Seung H. Kang, “Development of embedded STT-MRAM for mobile system-on-chips,” IEEE Transactions on Magnetics, Vol. 47, No. 1, January 2011, pp. 131-136.
Er-Xuan Ping is a managing director in the Silicon Systems Group at Applied Materials. He holds his Ph.D. in electrical engineering from Iowa State University.
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