Embedded Technology Forum
Friday, September 6th, 2013
Room 504 BC, 5F, TWTC Nangang Exhibition Hall, Taipei
|Theme: Bridging the Last Mile: Chip-to-Substrate Interconnections|
(1) Discover Killer Application for Embedded Die Packaging
(2) Supply Chain and World-wide Leading Progress of this Emerging Packaging
(3) Discuss the Cost / Technology Challenge & Potential Solution
Will "embedded die" be a cost-effective 3D solution? For potential mobile applications, embedded die has been considered another 3D-compatible technology and key element for miniaturization and ultra-thin 3D packaging. While several reconfigured wafer-molded or panel-level alternatives have been developed, remaining challenges still come from the process integration with known-good-die yield risk, precise die positioning, reliability issues and even supply chain R&R associated in the new business model.
To explore the path forward to cost-effective 3D approach, Embedded Technology Forum invites key contributors to share their latest achievements with technology progress in process & materials and re-visit the production readiness & cost structure.
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Forum Chair & Morning Session Moderator:
Afternoon Session Moderator:
Technical Sponsored by
Title / Speaker
08:30 – 09:00
09:00 – 09:10
Welcome / Opening Remarks
1. Dr. Rolf Aschenbrenner, Deputy Director, Fraunhofer IZM
09:10 – 09:40
Market Overview - Extension Embedded Technology to Wider Application
Mrs. Rozalia Beica, CTO & Business Unit Director, Yole Développement
09:40 – 10:10
Applications of Fan-Out Wafer Level Packaging
Dr. Beth Keser, Senior Staff Manager, Package Engineering, Qualcomm Incorporated
10:10 – 10:30
10:30 – 11:00
Embedded Component in Panel Production
Mr. Mark Beesley, COO Advanced Packaging, AT&S AG
11:00 – 11:30
Panel Level Embedded Technology
11:30 – 12:00
A Trace-Embedded Coreless Substrate Technique
12:00 – 13:30
13:30 – 13:40
13:40 – 14:10
Fan-out Wafer-level Technology – Extending Moore’s Law to the Packaging Domain
Dr. Raj Pendse, Vice President & Chief Marketing Officer, Product & Technology Marketing (PTM), STATS ChipPAC Ltd.
14:10 – 14:40
Solder Material Technology for Embedded Package
14:40 – 15:10
A New Embedded Package Structure and Technology for Next Generation of WLP, The Wafer Level Fan-out Package - WFOPTM
Mr. Akio Katsumata, General Manager Packaging Research & Development Center, J-Devices Corporation
15:10 – 15:40
Expectation of Embedded Device Technology and Key Challenging Area
Mr. Takashi Kariya, Division Manager, R&D Operation, Electronics Development Division, IBIDEN CO., LTD.
15:40 – 15:50
● Programs are subject to change without prior notice.
● All presentations will be conducted in English
● No recording/ photography during seminar.