SiP Global Summit : Embedded Technology Forum

 
 
Embedded Technology Forum
Friday, September 6th, 2013
08:30 –15:40 
Room 504 BC, 5F, TWTC Nangang Exhibitoin Hall, Taipei
Theme: 
Fan-out Wafer Level Pac
kaging & Embedded Substrate
 
Forum Objectives:

(1) Discover Killer Application for Embedded Die Packaging

(2) Supply Chain and World-wide Leading Progress of this Emerging Packaging

(3) Discuss the Cost / Technology Challenge & Potential Solution

Outline:

Will "embedded die" be a cost-effective 3D solution? For potential mobile applications, embedded die has been considered another 3D-compatible technology and key element for miniaturization and ultra-thin 3D packaging. While several reconfigured wafer-molded or panel-level alternatives have been developed, remaining challenges still come from the process integration with known-good-die yield risk, precise die positioning, reliability issues and even supply chain R&R associated in the new business model.

To explore the path forward to cost-effective 3D approach, Embedded Technology Forum invites key contributors to share their latest achievements with technology progress in process & materials and re-visit the production readiness & cost structure. 

 

 

Brought to you by    

SEMI Taiwan PKG&TEST Committee

Program Organizing Committee

Program Steering Committee

 


General Chair:
Dr. Ho-Ming Tong / 唐和明
, 
Chairman, SEMI Taiwan PKG&TEST Committee / General Manager & Chief R&D Officer, ASE Group

Forum Chair

Dr. Wei-chung Lo/ 駱韋仲, Director, Package Technology Div./EOL ITRI

Forum Co-Chair

Mr. Chia-Pin Lee/ 李嘉彬,   President, Unimicron Technology Corp. 欣興電子股份有限公司 總經理

Organized by
 
 
 
Sponsored by
 
 

 

Agenda
Time 
Title / Speaker

08:30 – 09:00

Registration

09:00 – 09:10

Welcome / Opening Remarks

09:10 – 09:40
Market Overview (Extension embedded technology to wider application)
Yole

09:40 – 10:20

Keynote Speech 


10:20 – 10:30
Break Time

10:30 – 11:00

Topic 1: Application - Cost Effective Technology Solution 

Dr. Beth Keser, Senior Staff , Advanced Packaging, Qualcomm

11:00 – 11:30

Topic 2: Application - Cost Effective Technology Solution

11:30 – 12:00

Topic 3: Technology – Panel Level

Dr. Dyi-Chung Hu, Sr. VP, R&D, Unimicron 

12:00 – 13:30
Lunch Break
13:30 – 13:40
Welcome Remarks
13:40 – 14:10
Topic 4: Technology – Wafer Level Fan-out
 Mr. Albert Lan / 藍章益, Sr. Director, Engineering Center -Customer Advanced Packaging, SPIL
14:10 – 14:40
Topic 5: Technology 

14:40 – 15:10
Topic 6: 

Fan-out Wafer Level Package


15:10 – 15:40

Topic 7: Embedded Substrate

15:10 – 15:40

Topic 8: Materials

CTO, Senju

● 主辦單位保留議程更改之權利。

 ● 論壇演講內容皆以英文為主。

 ● 論壇全程禁止錄音/攝錄影。

 

● Programs are subject to change without prior notice. 

 ● All presentations will be conducted in English

● No recording/ photography during seminar.

 
● Forum Fee : (TBD)