SiP Global Summit : 3D IC Technology Forum


 
 
3D IC Technology Forum
Thursday, September 5th, 2013
08:30 –17:00
Room 504 ABC, 5F, TWTC Nangang Exhibitoin Hall, Taipei
Theme :    (Challenges for) 3D IC - Standardization, Cost and Yield (TBD)
Forum Objectives:
(1) Review 2.5D/3D IC Market Situation
(2) Discuss Barrier(or Challenge) to Volume Adoption of 3D IC
(3) Best Practice Knowledge Sharing for Cost & Yield
(4) Discuss the Optimal Standardization on Eco-system and Process Flow. 
  
Outline:

While the whole supply chain is preparing for 3D IC readiness with a given developing infrastructure & facilities to support its go-to-market, and when 2.5D IC design had been adopted by advanced product. However, the ecosystem is looking forward to achieving a faster volume adoption and wider market penetration to ICT products.

Although many valuable perspectives had been addressed about 3D IC in recent years, this 2013 3D IC Technology Forum is to provide further guidance on the path between 2.5DIC and 3DIC from both market and technology drivers. The core issues of yield, standardization and cost will also be addressed to ensure maturity for high volume 2.5D / 3DIC production with TSV. 

Brought to you by
                           
                           
 
General Chair:
Chairman, SEMI Taiwan PKG&TEST Committee / General Manager & Chief R&D Officer, ASE Group
 
 
 
Forum Chair & Moderator: 
Mr. Mike Liang/ 梁明成, President, Amkor Technology艾克爾國際科技股份有限公司 總經理, Chairman, SEMI Taiwan PKG&TEST Committee                       
 
Forum Co-Chair(TBD)

Dr. CP Hung / 洪志斌, VP of Corporate R&D, ASE

 
Panel Discussion Moderator:(TBD)
Organized by
 
 
 
 
Sponsored by
 
  
Agenda
Time 
Title / Speaker
08:30 – 09:00
Registration 
09:00 – 09:20
Welcome / Opening Remarks
1. Executive, SEMI
2. Dr. Ho-Ming Tong / 唐和明, Chairman, SEMI Taiwan PKG&TEST Committee / General Manager & Chief R&D Officer, ASE Group
3. Mr. Mike Liang/ 梁明成, President, Amkor Technology艾克爾國際科技股份有限公司 總經理, Chairman, SEMI Taiwan PKG&TEST Committee
09:20 - 09:50
Opening Speech – Technology Overview
(From Advanced Package to 2.5D/3D IC)
 Mr. Choon-Heung Lee, EVP & CTO, Amkor 
09:50 - 10:20
Keynote Speech - 3D IC Last Mile to Product Adaption (Benefit/Advantage to consumer & system)
       
10:20 - 10:30
Break Time 
10:30 - 11:00
3D IC Market Opportunities
CEO,Yole
11:00 - 11:30

3D IC (Interposer & Stacking) Cost Effective Technology Solution-Foundry / OSAT 

Mr. Jerry Tzou, Deputy Director, Backend Technology and Service Div., TSMC

11:30- 12:00

3D IC (Interposer & Stacking) Cost Effective Technology Solution-Process, Equipment and Materials

 

12:00-13:30
Lunch Break
12:30-12:35
Welcome Remarks
13:35–14:05
DfM Overview & Design Readiness for Production or DfM Yield Overview & Enhancement for Production (back-up topic)
 
 
      
14:05–14:35
DfM & Technology Readiness - Test for TSV Perspective
Greg Smith, General Manager, Computing and Communications Business Unit, Semiconductor Test Division, Teradyne
14:35–15:05
DfM & Technology Readiness – Equipment /Process Perspective (Temp Bond/Debond)
 SUSS      
15:05–15:35
DfM & Technology Readiness – Materials Perspective (Micro Bump/Ball, Underfill/Molding, …)
 NAMICS       
15:35–15:45
Break
 15:45–17:00
 Panel Discussion:
“3D IC Supply Chain Synergy”

Moderator: Dr. Ian Chan, Hermes-Epitek 
Keynote Presentation: Dr. Tony Flaim, CTO, Brewer Science (20 mins)
Panelists: 
1.Dr. Steve Bezuk, VP, Qualcomm
2.Mr. Jerry Tzou, Deputy Director, Backend Technology and Service Div., TSMC
3.Dr. Ho-Ming Tong, General Manager & Chief R&D Officer, ASE  
4.Dr. Mike Ma, Vice President, Corporate R&D, SPIL
5.Mr. Choon-Heung Lee, CTO, Amkor
6.Teradyne or SUSS
7.Dr. Tony Flaim, CTO , Brewer Science
 17:00
 Adjournment
● 主辦單位保留議程更改之權利。
● 論壇演講內容皆以英文為主。
● 論壇全程禁止錄音/攝錄影。
● Programs are subject to change without prior notice. 
● All presentations will be conducted in English.
● No recording/ photography during seminar.

 
 
● Forum Fee : (TBD)