Beyond 193i and Sub-22nm: Tackling the Cost and Technical Drivers

By Debra Vogler, Instant Insight Inc.

The semiconductor industry is being driven by opportunities in mobility and cloud computing, but the road to providing cost-effective solutions for consumer electronics and high-end servers is a slow one right now. The economic realities are as daunting as the technological challenges associated with addressing new transistor architectures, new materials, the introduction of extreme ultraviolet lithography (EUVL), 3D ICs, and the transition to 450mm manufacturing - all occurring, more or less, in parallel.

Keeping in mind the serious R&D spending needed to develop these advances, the SEMICON West 2012 TechXPOTs on Enabling Sub-22nm with New Materials and Processes (Tuesday, July 10, 10:30am-12:30pm), and Lithography: Extending Double-patterning, Industrializing EUV, and Complementary Technologies (Wednesday, July 11, 10:30am-12:30pm) offer an opportunity to discuss how suppliers and semiconductor manufacturers can together tackle the multiple imperatives facing the industry. These are just some of the pressing technical and cost drivers that will be discussed.

Lithography Choice is Cost-Driven

As with most new technologies in the semiconductor industry, cost of implementation in high-volume manufacturing (HVM) is the main driver - and lithography below 22/20nm is no different. Although much work has gone into EUVL, there are still those who are not entirely certain it will be ready in the most cost-effective manner for HVM. Some are banking on using 193 immersion (193i) lithography until it completely runs out of gas, and others are putting efforts into e-beam direct write (EBDW) lithography as well as into the new kid on the block, directed self-assembly (DSA). Each of these technologies has advantages and disadvantages. Many experts agree on one point that is probably best summarized by Stefan Wurm, director of lithography, at SEMATECH. “Everything is cost driven and the cost structure is different for different players,” Wurm told SEMI. “People will try to push existing technologies as far as they can go as long as they are cost-effective.”

 According to Yan Borodovsky, Intel Senior Fellow and director of advanced lithography, the company is using 193i to pattern critical layers, aided with pitch division as well as new materials and computational lithography, and will continue to do so until additional solutions become available that are commensurate with the CoO to sustain HVM. “If these other technologies (EUV and EBDW) do not materialize, Intel will continue to use 193i,” said Borodovsky. While the company is able to use 193i down to the 10nm node if it must, it is also working on possible lithography solutions below 10nm, though potential solutions at 7nm cannot be disclosed at this time.

 EUVL: It Works

With six NXE:3100 EUVL systems out in the field (being used for development work at end users’ sites), ASML’s Hans Meiling, senior director, product management EUV, is clear about one thing: on overlay and imaging - two key drivers for end users - the technology is in good shape. “There are no showstoppers in these areas,” noted Meiling. “The productivity is the cost issue - it’s not a blocker of the technology.”

Later in 2012 the company will be shipping the NXE:3300B. This newest version will have improved resolution (0.33NA, 22nm hp; 18nm hp with off-axis illumination [OAI]), increased transmission for higher productivity at higher dose, and the capability for OAI without energy loss, as well as a reduced footprint. The overlay will be 3.0nm/dedicated chuck overlay (DCO) and 5.0nm/matched machine overlay (MMO), respectively. The throughput for the 3300 will be 125wph at 15mJ/cm².
   
In terms of cost, ASML’s data comparing various lithography options indicates that EUVL provides a more cost-effective alternative.

SOURCE: ASML, presented at SPIE Advanced Lithography Conference, 2012

For one, by using a single-exposure system, the design restrictions necessary when using immersion and double-patterning together are avoided. Also eliminated are the many extra process steps required when using double-patterning (strip/clean, etch, and so on).

Maskless Lithography: A More Cost-Effective Choice?

Not everyone has been waiting for the promise of EUVL to become cost-effective, however. The IMAGINE Program headed by CEA-Leti is charged with developing and industrializing electron beam high-throughput maskless lithography (ML2) developed by MAPPER Lithography. Leti recently announced that the program achieved 22nm dense lines and spaces and 22nm dense contact holes in positive chemically amplified resist. These results meet the industry requirements for the next-generation 14nm and 10nm logic nodes according to the consortium. Serge Tedesco, Leti’s lithography program manager, explained that even if EUVL reaches its anticipated levels of productivity, he doesn’t see how it will be cost-effective for low-volume production, particularly for those foundries that have a large number of different designs with a low number of wafers per mask. “E-beam will cost less and foundry people will have an ever more difficult choice based on cost,” he said. When you add the costs of prototyping and device development, there are more reasons for the interest in a maskless solution on the part of foundries such as TSMC and STMicroelectronics. Even some logic device manufacturers are interested in the maskless e-beam technology, said Tedesco.

While there has been discussion in the industry about the possibility of companies that have the large volumes associated with memories - and that also run logic and have a foundry business (e.g., Samsung) - running both EUVL and e-beam lithography, Tedesco acknowledged that it won’t be easy running two different lithography technologies in the same fab. “But people think more and more that, depending on the application, it could be possible,” said Tedesco.
IMAGINE Program members come from 13 different companies including TSMC, STMicroelectronics, TEL, Sokudo, TOK, JSR, Dow EM, Nissan Chemical, Synopsys, Aselta Nanographics, and Mentor Graphics. With many of the participants also active in EUVL development, it stands to reason that the competition for funding and human resources is a juggling act. Still, Tedesco is hopeful that discussion about e-beam lithography will convince the industry to continue funding. “We really need to raise the interest,” he said.

Next on the agenda for the IMAGINE Program is building a full-field pre-production tool with a 1wph throughput with stitching capability. Tedesco reports that all of the system modules are under development at MAPPER; the exact timing of when the 1wph tool will be completed and delivered to Leti is not yet available, though Tedesco says it will be delivered in the first half of 2013. Integration of the modules will start by the end of 2012. The tool will have 13,000 beams - though in the beginning, only 10% of the beams will be used while beam uniformity issues are addressed. The next step is to go to a 10wph tool in which all 13,000 beams will be used. After that, a 100wph tool is planned; it will be accomplished by clustering 10 systems (each system having 13,000 beams) together. It is intended that the 100wph tool will be the production version said Tedesco.

A Different View of Cost Issues

Donis Flagello, NRCA Fellow at Nikon Research Corporation of America, is of the belief that EUVL is here to stay: “there’s been too much invested and too many people bought machines,” he told SEMI. “I think some of the bigger players out there will accept running EUV machines slower because the options don’t look that good.” But he also believes that because the industry has come up against the costs of EUVL and the realities, it’s prompted a push to pursue parallel paths and backup plans. One example is DSA. Flagello calls the move of DSA out of academia and into development houses at chip fabs amazing. “I’ve never seen that happen so fast,” he said. “I don’t know at what point people will make a decision...I think people will keep working in parallel at least for the next couple of years.”

Regarding e-beam lithography, Flagello notes that it may not be necessary for the MAPPER team to try and push for a 100wph tool to compete directly with EUVL. “If you can build a machine that gets 5wph, you will have your foot in the door and you can make lots of wafers.” He suggests that e-beam lithography will be more of a complementary technology.

Lithography: Building an Infrastructure

SEMATECH has been contributing to building an EUVL infrastructure via its Mask Blank Development Center (MBDC) and its Resist and Materials Development Center (RMDC). The consortium’s two microfield exposure systems (METs) have been enabling the resist and materials infrastructure to introduce EUV at the 22nm hp while exploring extendibility to 16nm. “The METs have operated at higher uptime, and utilization of RMDC tools has increased, as has the total of imaged wafers across all tools,” noted Wurm. The consortium has evaluated more than 2000 new EUV materials formulations that target the sub-22nm hp nodes. According to SEMATECH, the RMDC’s capabilities allow resist and material suppliers to gain access to the highest-resolution optical imaging available as well as to the high throughput that resist and materials samples require for early stage development. Wurm also reports that the MBDC has demonstrated new champion data of a total of 6 particles on an EUV mask blank at >50nm sensitivity, which surpasses the best recorded results of 26 particles at >50nm sensitivity. 

While work on resists and masks throughout the industry has been ongoing, experts say that more work needs to be done to study the physical properties of mask materials. According to Franklin Kalk, EVP & CTO at Toppan Photomasks, such properties as refractive indices and elemental composition need to be evaluated. Similarly, Kalk is interested in mask durability under HVM conditions, which is not possible until there is a source with the requisite power available.

A breakthrough in resist development was reported at this year’s SPIE Advanced Lithography Conference (2/12-2/16/12, San Jose, CA), whereby 16nm hp at 33mJ/cm² was achieved. However, to meet EUVL throughput targets, the sensitivity has to go below 20mJ/cm². Some experts question whether the usual trade-off among resolution, line-edge roughness, and sensitivity can be met. For example, Kalk isn’t sure resists in the 10-15mJ/cm² range are doable for EUV. “There won’t be enough photons to give good line-edge roughness (LER) at that kind of dose,” said Kalk. “I think we’ll probably be looking more at about 25mJ/cm² resists.”

New Materials and Processes for Sub-22nm Devices

Intel has continued its pursuit of improved transistor performance - particularly at low voltages - with its tri-gate architecture. And though such performance at low voltage and low power are needed for consumer electronics, Kaizad Mistry, VP, director of logic technology integration at Intel, told SEMI that it’s also required for high-performance servers. The company plans on using the tri-gate structure, which was announced in 2011, not only for the 22nm node, which is already in production, but also at 14nm. According to Mistry, the company expects to be in HVM for 14nm by 2H13.

Mistry noted that there are advantages to being an IDM when bringing new technologies to market. “Whether it’s design tools that need to change...or mask making that needs to change, or fab process tools that need to change - we can adapt and get those things done more easily as an IDM,” said Mistry. He added that collaborating internally is easier than collaborating across corporate boundaries, thereby facilitating bringing new devices to market sooner. 

Continuing transistor scaling beyond 22nm will require not only the eventual adoption by all of a type of 3D device (e.g., FinFETs, tri-gates), but the use of high-mobility channel materials (Ge or III-V materials) on silicon to meet power dissipation requirements. According to Raj Jammy, VP, emerging materials and technologies at SEMATECH, the point at which a given company will adopt a 3D transistor architecture along with high-mobility channels depends on its specific products and applications. Jammy, however, believes the point at which everyone will have to switch to 3D+high-mobility will most likely occur at 11nm and below.

The move to Ge and III-V materials will be challenging and Jammy says that in order for the materials to be ready in time, the industry has to start thinking about tackling the challenges now. Among the challenges are the deposition of high-quality III-V layers on top of silicon - and doing so cost-effectively with low defect density. Additionally, the making of junctions will be different when using III-Vs because implantation cannot be used. Other challenges include selecting the contact material: gold is used now with III-V materials that are on III-V substrates; but gold cannot be used with III-Vs on silicon because it diffuses rapidly into silicon and changes the device characteristics. Despite the daunting list of challenges, experts maintain that the benefit of using high-mobility materials is the ability to enable greater functionality (for example, SoC) on chips. 

One technique being evaluated by imec researchers - aspect ratio trapping (ART) - is expected to offer a lot of flexibility for heterogeneous integration. According to Aaron Thean, director, logic program, at imec, ART is a way of growing highly mismatched materials in tight trenches. The defects that form can be terminated on these highly confined structures, he said. So as the crystal grows up the trench, the material will relax, forming defects that tend to terminate on the sidewalls of the trenches. At some point, most of the defects will end up on the sidewalls leaving a less defective material at the top of the growth, explained Thean. This less defective material can then be used as the channel material for the device. The flexibility arises from the ability to use ART to  grow different materials in different trenches on the same wafer/chip. So for example, Thean noted that one could grow III-V in some trenches, and in other trenches one could grow Ge - all on the same wafer/chip.

The College of Nanoscale Science and Engineering (CNSE) at the University at Albany is also working on sub-20nm technologies. The research organization is collaborating with equipment suppliers to evaluate new techniques for ultra-shallow junctions. Christopher Borst, assistant VP for module engineering at CNSE, told SEMI that Nissin Ion Equipment is working with CNSE to engineer the incorporation of a Si:C layer into the source/drain region of NMOS transistors to improve drive current. “The joint work evaluates Si:C stressor layer formation by molecular carbon (cluster carbon) implantation with a suitable combination of anneal conditions,” reported Borst. “The collaboration is intended to study the combined effect of C cluster implant followed by a rapid thermal anneal and subsequent laser anneal for dopant activation.”

According to Borst, among the requirements for this combined process is that it must result in a beneficial strain property and defect-free recrystallization of the Si:C layer.

CNSE is also conducting TCAD simulation of nonplanar device geometries scaled to 20nm FinFET widths and below.  “These simulations include Monte Carlo and analytic solutions for ion implantation and subsequent diffusion using varied spike and laser anneal combinations to optimize active dopant profiles for nonplanar structures,” said Borst. “The physics and electrical results from these studies are evaluated and verified using nonplanar structures in silicon and then extrapolated to simulated III-V device structures.”

To address scaling down to 1Xnm and below, CNSE is also developing alternative channel FinFET integration schemes by using an infrastructure of advanced process tooling available at the college (e.g., litho, dry etch, wet etch, and thin film). “We are creating extremely aggressive test structures both in bulk material architectures and in replacement gate strategies,” reports Borst. “This will allow us to explore Ge and eventually III-V FinFET devices at sub-10nm dimensions.”

Practical Considerations

As the industry works to develop the materials and processes for advanced ICs, there are some practical considerations - namely, the design of process equipment - that also have to be addressed. And cost is, again, a primary driver. As features become ever smaller, the impact of impurities and defects on yield become even more significant below 22nm. Taking additional steps to prevent flaking, particulates, and delamination off process chamber walls is critical at 20nm and below, but one of the most desirable materials for this task that has a low erosion rate (yttrium, according to Advenira SVP, business development, Andrew Skumanich) is also the most expensive. Other choices such as a standard aluminum oxide or aluminum nitride, are relatively inexpensive, but not effective enough below 20nm.

Advenira, has developed a liquid deposition process in which the liquid is converted to a solid that is comprised of glass-like elements: a mix of silicas, carbides, and nitrides. The exact composition depends on the part/application (shower heads vs. chamber rings) and what kind of protection is required. The coating is conformal, said Skumanich, and it can be tuned such that thermal expansion coefficient matching can be accomplished. This feature is important to prevent problems with process chamber components that see frequent thermal cycling (i.e., mismatched coatings delaminate, creating particulates). Skumanich also noted that the company’s process provides a two orders of magnitude improvement in erosion resistance to the most aggressive fluorine chemistry compared to standard composites, yet is lower cost than Yt-based approaches.

Debra Vogler is president of Instant Insight Inc.; email debravogler@me.com 

June 2012