What’s New in 3DS-IC and HB-LED Standards? SEMICON West Preview

What’s New in 3DS-IC and HB-LED Standards? SEMICON West Preview

The North America Standards meetings at SEMICON West will take place on July 9 - 12 in San Francisco, California.  This meeting set will host 14 committees and over 70 task forces.  The Standards Registration Desk (including badge pick-up) will be located on the 4th floor, outside of the Pacific A meeting room.  Learn more and register today!

Read more about what is happening in Standards. This lengthy article covers:

  • Chart detailing all Standards meetings at SEMICON West

  • SEMI 3DS-IC Standards Activities in North America

  •  Organization Chart for SEMI 3DS-IC North America and Taiwan

  • SEMI HB-LED Standards Activities in North America

  • 3DS-IC and HB-LED Activities in Other Regions

  • Standards Resources

NA Standards Meetings at S/West 2012

SEMI 3DS-IC Standards Activities

The North America (NA) Three-dimensional Stacked Integrated Circuits (3DS-IC) Committee and its associated task forces (TFs) will be meeting on Tuesday, July 10 at the San Francisco Marriott Marquis.  The current meeting schedule is as follows:

Tuesday, July 10:

  • Inspection & Metrology Task Force (8:00 AM to 10:00 AM)
  • Bonded Wafer Stacks Task Force (10:00 AM to 12:00 Noon)
  • Thin Wafer Handling Task Force (1:00 PM to 3:00 PM)
  • NA 3DS-IC Committee (3:00 PM to 5:00 PM)

For those interested in attending these meetings, please check the on-site schedule board for meeting information or for any last minute schedule changes.

The Inspection & Metrology Task Force will be reviewing the voting results of SEMI Draft Document 5269A, New Standard: Terminology for Through Silicon Via Geometrical Metrology which was issued for the Cycle 4 voting period

Document 5269A provides a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs). The Inspection & Metrology Task Force recognized the need for such a standard because different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top CD, top diameter, top area, depth, taper (or sidewall angle), bottom area, bottom CD, bottom diameter, and possibly others. However it is currently difficult to compare and/or correlate results from the various measurement technologies for various TSV dimensions. In some cases certain parameters may be described by similar names, but are actually different aspects of the TSV geometry. Other characteristics of TSV metrology, such as electrical metrology, could be addressed in a future activity.

The Inspection & Metrology Task Force will also be discussing at SEMICON West 2012 its progress on other standardization activities:

  • New Standard: Guide for Measuring Voids in Bonded Wafer Stacks (SNARF # 5270)
  • New Standard: Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks (SNARF # 5409)
  • New Standard: Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures (SNARF # 5410)

Finally, at its previous face-to-face meeting, the Inspection & Metrology Task Force welcomed Victor Vartanian (SEMATECH) as its newest co-leader serving with Yi-Shao Lai (ASE), David Read (NIST), and Chris Moore (Semilab).

The Bonded Wafer Stacks Task Force will be reviewing the voting results of SEMI Draft Document 5173A, New Standard: Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack which was issued for the Cycle 4 voting period

Document 5173A aims to provide the 3DS-IC community with the tools needed to define wafers used in each step of a 3DS-IC process.  Four classes of materials, each of which is commonly used in the production of 3DS-ICs, are discussed in this document: 

  1. Polished single-crystal silicon wafers for 3DS-IC applications
    1. Device Wafers
    2. Carrier Wafers
  2. Glass wafers for 3DS-IC applications.
    1. Device Wafers (reserved for future work)
    2. Carrier Wafers
  3. Non-stacked processed wafers intended for additional 3DS-IC processing steps.
  4. Bonded-wafer stack composed of two or more wafers.

Each of the above is provided as an order form, which contains entries for all of the information needed to describe the wafer or wafer stack to enable 3DS-IC processing.

The Bonded Wafer Stacks TF will also be discussing its progress on other standardization activities including SNARF # 5174, New Standard: Specification for Identification and Marking for Bonded Wafer Stacks.

The Thin Wafer Handling TF will be discussing its progress on SEMI Draft Document 5175, New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers.  The task force welcomed Rich Allen (SEMATECH) as its newest co-leader serving with Urmi Ray (Qualcomm) and Raghunandan Chaware (Xilinx).

The last NA 3DS-IC Committee and task force meetings were held on April 3 in conjunction with the NA Standards Spring 2012 meetings in San Jose, California.  The minutes of the NA 3DS-IC Committee meeting on April 3, 2012 are available on the SEMI Standards website.

Standards Org Chart

SEMI HB-LED Standards Activities

The North America (NA) High-Brightness Light-Emitting Diodes (HB-LED) Committee and its associated task forces (TFs) will be meeting on Wednesday (July 11) and Thursday (July 12) at the San Francisco Marriott Marquis.  The current meeting schedule is as follows:

Wednesday, July 11

  • Equipment Automation Task Force / Hardware Working Group (8:00 AM to 5:00 PM)

Thursday, July 12

  • Impurities & Defects Task Force (8:00 AM to 9:00 AM)
  • Wafer Task Force (9:00 AM to 11:00 AM)
  • Equipment Automation Task Force / Software Working Group (11:00 AM to 3:00 PM)
  • NA HB-LED Committee (3:00 PM to 5:00 PM)

For those interested in attending these meetings, please check the on-site schedule board for meeting information or for any last minute schedule changes.

The HB-LED Hardware Working Group (WG) of the Equipment Automation TF will be reviewing the voting results of SEMI Draft Document 5420, New Standard: Specification for 150 mm Open Plastic and Metal Wafer Cassettes Intended for Use for Manufacturing HB-LED Devices which was issued for the Cycle 4 voting period

Document 5420 was developed to define standards for cassettes used to handle 150 mm sapphire wafers in HB-LED manufacturing.  To minimize impact to the industry the TF is leveraging existing 150 mm silicon cassette standards with minor revisions.  This will allow interoperability with existing 150 mm equipment and any other 150 mm compatible products.  Considerations were taken around the cassette’s pocket size and spacing so that the sapphire wafers can be successfully transferred between cassettes with automated handling equipment.

A cassette standard will also enable standardization of load ports and transport systems. This will result in direct and indirect cost savings throughout the whole supply chain, less risk during ramp up and less effort for integration of the production line.

Also during SEMICON West, the HB-LED Hardware Working Group will continue its development of the 150 mm load port interface specification with plans to complete the draft proposal by Fall 2012.

The HB-LED Software Working Group of the Equipment Automation Task Force will be discussing its progress on reviewing existing SEMI equipment communication standards and identifying required changes for HB-LED manufacturing.  The Task Force will first look into basic communications standards then onto extended functionalities on SECS-II/GEM.  The initial draft is scheduled for Fall 2012.  Eventually, the task force will look into SEMI Interface A standards (i.e., E120, E125, E132, and E134) and investigate how these can be leveraged for HB-LED manufacturing.

The Impurities & Defects Task Force will be reviewing inputs received thus far on the Defect vs. Inspection Technique Relevance Survey which was deployed in mid-June.  The survey aims to identify sapphire wafer defects that are relevant or important to HB-LED manufacturing as well as inspection techniques that can be applied to identify, measure, or prevent such defects.

The HB-LED Wafer Task Force will be reviewing the voting results of SEMI Draft Document 5265A, New Standard: Specifications for Sapphire Wafers Intended for Use for Manufacturing High Brightness-Light Emitting Diode Devices which was issued for the Cycle 4 voting period

Sapphire wafers are widely used in producing HB-LED devices that are used in multiple applications e.g. LCD backlights, signage and solid-state lighting.  Improving manufacturing efficiency and cost reductions are critical elements in enabling continued industry advance.  150 mm sapphire wafers represent a key inflection point to obtain these goals. 

SEMI Draft Document 5265A defines and specifies the physical geometry of 150 mm diameter sapphire wafers used in HB-LED manufacturing.  Nominal values and tolerances addressed include: general characteristics, wafer preparation characteristics, dimensional characteristics, and front surface inspection characteristics.  Standard specifications and a specification format for order entry are included to cover all requirements of the industry.  Document 5265A also includes proposed specifications for 100 mm diameter sapphire wafers.

The Wafer Task Force will also be discussing at SEMICON West 2012 its progress on the wafer marking experiment characterizing mark survivability, mark width, and depth.

The last NA HB-LED Committee and task force meetings were held on April 4-5 in conjunction with the NA Standards Spring 2012 meetings in San Jose, California.  The minutes of the NA HB-LED Committee meeting on April 5, 2012 are available on the SEMI Standards website.

3DS-IC and HB-LED Activities in Other Regions

Taiwan 3DS-IC Activities

 Earlier this year, the Taiwan 3DS-IC Committee approved the formation of its second task force on middle end process.  The Middle End Process Task Force was chartered to develop standards and define specifications for middle-end process (MEOL) related manufacturing flow.  The task force will initially focus on the middle-end process on wafers with or without TSVs, including post final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line (RDL) formation and carrier de-bond. 

The Testing Task Force was the first task force chartered by the Taiwan 3DS-IC Committee in late 2011 to develop standards, guidelines, and/or specifications for electrical testing related activities used in 3DS-IC manufacturing for the ultimate goal of yield enhancement.

Taiwan LED Safety Task Force

 The LED Safety Task Force was chartered in late 2011 under the Taiwan EHS (Environmental, Health, and Safety) Committee to develop specifications and guidelines related to LED manufacturing equipment.  The activities of the task force will result in the development of an EHS industry standard which equipment suppliers, raw material suppliers, module makers and other involved parties can find conformity.

SEMI Standards Resources

For more information or to participate in any SEMI 3DS-IC and/or HB-LED Standards activities, please contact the following SEMI staff:

SEMI Standards 3DS-IC Google Site | SEMI Standards HB-LED Google Site

 

July 2, 2012