Back-End Perspectives on 450mm Wafers and Emerging Panel Scale Packaging Technologies
By Yann Guillou, SEMI Europe
While many in the industry take a front-end view of 450mm, it will create new challenges for assembly and packaging. Key issues include: What new challenges will emerge related to the packaging of 450mm wafers? Are the issues already addressed by today’s back-end players? Are disruptive technologies expected? Are there opportunities for new entrants?
SEMI Europe recently hosted a workshop in Grenoble “Beyond 300mm: Packaging Challenges and Opportunities for 450mm Wafers and Panel Scale Solutions” which offered both perspectives and answers to some of the complex wafer-size transition issues facing the semiconductor industry. The workshop covered the core topics of packaging of 450mm wafers and panel scale solutions. Over 50 experts and decision makers from international companies participated in the first edition of this initiative. Industry players from both the front-end and back-end worlds gathered under “the same roof” to share information about technologies that are increasingly overlapping, with a special focus on obtaining a status report on the situation of packaging and assembly developments related to the 450mm transition.
450mm and Packaging
In the “450mm and Packaging” session, Michael Liehr, GM, Global 450 Consortium (G450C) and VP, research at the University of Albany College of Nanoscale Science and Engineering (CNSE), presented on the G450C, a public-private partnership program to enable a coordinated transition to 450mm wafers. Positioned as an umbrella initiative with six core members including TSMC and Intel, the consortium will collaboratively work with suppliers to develop and test 450mm equipment. The consortium is at present collecting RFQ answers from suppliers for tool installation starting in 2013 in CNSE facilities. Liehr underlined his willingness to share the progress of this initiative with the European Equipment and Material actors that would play a central role in 450mm transition.
SOITEC informed the attendees about the benefits that can bring SOI technologies, especially for the sub 32nm node. Daniel Delprat, Advanced R&D manager, described various 450mm projects involving SOITEC such as EEMI 450 and SOI 450. He presented some successful results of their Smart CutTM technology on 450mm wafers done in collaboration with EV Group.
Bill Shaner, VP and GM at Entegris, focused on progress made by Entegris in the last few years in the field of 450mm wafer transition. Presenting 450mm FOUP and MAC developed by Entregris, he displayed impressive experimental videos showing the fragility specificities of 450mm wafers under heavy shock conditions.
Guy Dubois, founder and GM of GDCL Management, Delpu from Recif Technologies, Wimplinger from EV Group and Rouzaud from CEA-LETI were on the concluding panel discussion “450mm packaging Challenges and Opportunities for Equipment and Materials Suppliers” with Shaner. Dubois contributed with Future Horizons and Decision to a report which was submitted to the European Commission. He underlined the willingness of Equipment and Materials suppliers to be fully associated with this wafer size transition that is identified as a “game changing” event and an opportunity for Europe to maintain its leadership position in “More than Moore” and eventually re-enter the “More Moore” manufacturing landscape.
Andre Rouzaud, deputy VP Microsystem, CEA-LETI confirmed that the 450mm wafer transition will happen and explained the role that Research and Technology Organizations (RTO) such as LETI can play in 450mm process modules development and with Equipment and Materials collaborations. EVG announced they have already developed a first machine for SOI wafers and made the investments to develop additional equipment. While he could not disclose details, Markus Wimplinger added that his company had a clear internal roadmap for 450.
Guilhem Delpu presented the active role of Recif Technologies in 450mm with various ongoing projects on wafer handling systems, including the NGC450 project led by his company. Delpu as well stressed the crucial role of collaboration among the players to make the 450mm transition economically viable for everyone in the supply chain.
Panel Scale Packaging Technologies
As a normal evolution of packaging to help in reducing cost, speakers presented their perspectives on large scale packages. Issues included: What is the situation today in terms of development and maturity? Can large size be fabricated with high throughput and good yields? Speakers in this session talked about technologies such as fan-out wafer-level packages on rectangular rebuilt wafers, embedded die in laminate, glass carrier with and without vertical vias enabling 2.5D integration. Executives from Yole, ASE, STATSChipPac and AT&S presented their views.
As an introduction to the Panel Scale Packaging Technologies session, Jean-Marc Yannou, president, IMAPS France and senior analyst at Yole Developpement, described the technologies that can be categorized under the name “Panel Scale Packaging Platforms.” He started with the embedded Wafer Level Ball Grid Array (eWLB) technology developed by Infineon and under mass production at several IDMs and OSATS for a couple of years. He presented the embedded IC in laminate substrate technology that is of growing interest for small die and relatively low I/O count. Glass and Silicon interposer were also addressed. Application space, main providers and cost comparisons were presented as well as the future technology trends to further reduce their cost by going larger. The main conclusion was that two streams — based on either a 450mm round wafer shape or a rectangular panel shape — were under investigation by players.
Two top-tier OSATS manufacturing these technologies shared their positioning and perspectives. Wirtz and Appelt, business development executives from respectively STATSChipPac and ASE Group, each presented their company’s roadmap related to panel scale packaging technologies. Agreeing with Yole, Heinz-Peter Wirtz confirmed the eWLB cost reduction path by use or larger rebuilt format than 300mm (larger than 300mm rebuilt wafer or rectangular panel format).
Bernd Appelt presented ASE Group Fan-Out Panel developments for low pin count and high power applications, reliability results and a detailed roadmap. He confirmed ASE’s commitment to the development of these embedding technologies into market.
COO Mark Beesley from AT&S, one of the leading chip embedding providers, described the benefits of their proprietary technology called ECP. He reminded the audience of the intrinsic 3D capabilities of ECP enabling to stack passives on top of the IC. He also described some supply chain considerations linked to this technology before showing the various project AT&S were ramping up.
In conclusion, with new packaging technologies manufactured at panel level and with the transition to 450mm wafers, collaborations and exchanges between industry players are needed to develop cost effective and timely solutions. The workshop highlighted the strengths of European equipment and materials companies and the opportunities for complementary development for panel scale technologies and 450mm packaging.
The second Beyond 300mm Workshop will take place in Grenoble in September 2013.
June 5, 2012