Packaging Community Takes on New Challenges through Industry Collaboration
As the semiconductor industry responds to increasing demands for lower power, higher performance and reduced form factor, packaging technologies are increasingly important. This enhanced importance in the micro-electronics food chain is mirrored in a growth of the different segments of the packaging market. According to the recently updated Global Semiconductor Packaging Materials Outlook, materials are forecast to grow from $23.4 billion in 2011 to $23.9 billion in 2012. Packaging and Assembly equipment will also continue to stay above the $3 billion mark it exceeded in 2010.
Packaging and the 450mm Wafer Transition
As a number of IDMs and foundries look toward a wafer size transition to 450mm, the packaging community has begun to look at the implications. The largest challenge, capital investment and related ROI, is similar to that of the front-end transition. Wafer level packaging processes will also incur a premium over 300mm. In particular, wafer bumping will require additional complexity for plating and RDL at 450mm, not to mention costs for process development. Wafer thinning for packaging and handling throughout the back-end processes will also present large challenges. Wafer die attach and dicing challenges are perhaps not as significant, but will need to be addressed nonetheless.
Fabless companies, IDMs, foundries and outsourced system assembly and test houses (OSATs) are all keen to take advantage of this growing market and deliver innovative solutions to customers. And innovative solutions are coming — everything from 3D-ICs with thru-silicon vias (TSVs) to interposer solutions to innovative new approaches to flip-chip and wafer-level packaging. Consumers are driving the market in these new innovative directions, but those same consumers are not interested in spending any more for the latest upgrade to their smartphones, tablets and other devices.
Companies throughout the packaging value chain are increasingly using various collaborative mechanisms to make sure they are well placed to bring their innovations to market. SEMI members, committees and volunteers form one vital nexus for this collaboration. SEMI packaging program and/or standards committees exist in every semiconductor manufacturing region in the world. The committees are the collaborative force that brings standards, world-class technical and business sessions and networking opportunities to the industry. These activities bring the industry closer to the goal of realizing cost-effective adoption of the new technologies that enable the next generation of devices for consumers.
International Standards for Packaging and 3D-IC
“International manufacturing standards are essential pre-competitive consensus-based agreements needed to realize new technologies, such as 2.5D interposer and 3D with TSVs, and efficiently bring from early-stage development to volume production,” says Jonathan Davis, president of SEMI’s Global Semiconductor business.
Over 350 packaging industry experts from around the world collaborate to develop packaging and 3D-IC standards. Recently, the Packaging Standards Committee has published a new tape frame standard for 450mm
The new 3DS-IC Standards Committee has added a Taiwan committee to the organization, and will be sending out its first documents – one on terminology for TSVs and one on parameters for bonded wafer stacks – both going out for ballot early this year.
Business and Technical Programs
Upcoming Packaging Events
The collaborative work of the packaging programs committees has also produced outstanding sessions focused on the intersection of semiconductor packaging technology and business. In the second half of 2011 alone, the Americas Advanced Packaging Committee developed sessions which brought together industry leaders in 3D and 2.5D as well as heterogeneous integration of devices, while at the same time keep a focus on developments on packaging technologies that are needed in the near term. The SEMI Taiwan Packaging & Testing Committee developed the inaugural SiP Global Summit, which was a three-day intense look at 3D-IC packaging and test technologies as well as embedded substrates. The Advanced Packaging Committee of Europe delivered two half-day sessions at SEMICON Europe which took a hard look specifically at manufacturability with respect to technologies, materials, processes and equipment. And the Japan Packaging Committee developed two sessions of strong technical content covering 3D-ICs, TSVs, system scaling and integration, and interconnect in conjunction with the SEMI Technology Symposium (STS).
The packaging programs committees around the world continue to develop innovative and up-to-date content for programs going into the New Year (see “Upcoming Packaging Events”).
Far from being a series of closed meetings, the members of the packaging community that make up the various committees around SEMI enjoy a variety of networking activities in conjunction with the committee work. From discussions in informal meetings to receptions and side events held alongside sessions, participants from system companies, fabless, IDM, foundries, OSATs, equipment and materials manufacturers have an opportunity to share viewpoints and create an agenda for tomorrow’s packaging technologies.
Market Research Study Available
A recently completed market research study on packaging, the Global Semiconductor Packaging Materials Outlook—2011-2012 Edition, produced by SEMI and TechSearch International, is now available. In developing this report, over 140 in-depth interviews were conducted with semiconductor manufacturers, packaging subcontractors and packaging materials suppliers throughout the world.
To order your copy of the report, please contact Dr. Dan P. Tracy, research development director, Industry Research and Statistics, SEMI via email at email@example.com, or telephone 1.408.943.7987 or facsimile 1.408.943.7915. You can also click here for sample, pricing, and ordering information.
January 10, 2012