3DS-IC Standards Updates – December 2011

3DS-IC Standards Updates – December 2011

By Paul Trio, SEMI

NA 3DS-IC Committee

The North America 3DS-IC committee and its three task forces – Bonded Wafer Stacks, Inspection & Metrology, and Thin Wafer Handling – met on October 25 in conjunction with the NA Standards Fall 2011 meetings in San Jose, California.

The Bonded Wafer Stacks TF is nearing completion in its development of SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack.  Current wafer standards (e.g. SEMI M1) do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits (3DS-ICs).  3DS-IC processes may require starting materials – silicon and glass wafers – with different tolerances for dimension and material than those specified in SEMI M1 and SEMI M24.  Further, in each step of a 3DS-IC process, the incoming material must be specified in terms of wafer dimension and materials present.  Wafer thickness, edge bevel, notch, mass, bow/warp and diameters change when wafer stacks are bonded, debonded, and when wafers incorporated into stacks are thinned.  Further, these parameters will change for a single wafer stack during process.  This document provides the required properties of both silicon (“device”) wafers and glass (“carrier”) wafers to be used in 3DS-IC applications.  Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well.  The task force plans to submit Ballot 5173 for the Cycle 1, 2012 voting period. 

The Inspection & Metrology TF has completed its development of SEMI Draft Document 5269, New Standard: Terminology for Through Silicon Via Metrology.  Different technologies can measure various geometrical parameters of an individual through silicon via (TSV), or of an array of TSVs, such as pitch, top CD, top diameter, top area, depth, taper (or sidewall angle), bottom area, bottom CD, bottom diameter, and possibly others.  However, it is currently difficult to compare and/or correlate results from the various measurement technologies for various TSV dimensions.  In some cases, certain parameters may be described by similar names, but are actually different aspects of the TSV geometry.  Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.  The purpose of this document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). The task force will submit Ballot 5269 for the Cycle 1, 2012 voting period.

The Thin Wafer Handling TF continues its development of SEMI Draft Document 5175, New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers.  Current standards for wafer transport and storage containers (e.g., shipping boxes, FOUP, FOSBs) do not adequately address the reliable storage and transportation of thin wafers and dice on tape frame used in 3DS-IC manufacturing.  Wafer thicknesses of 30-200 um will need significant changes to the current design criteria of current wafer transport and storage containers.  Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers (i.e., transportation/vibration and mechanical shock requirements).  The task force plans to complete development of Draft Document 5175 and submit for balloting in Q1, 2012.

The Cycle 1, 2012 voting period begins January 17 and ends February 16. SEMI Standards activities are open to all interested parties, but you must be a registered SEMI Standards Program Member to participate in SEMI Standards meetings and to vote on ballots.  Register today!

The next meeting for the NA 3DS-IC committee and its task forces is scheduled for April 3 in conjunction with the NA Standards Spring 2012 Meetings in San Jose, CA.

Taiwan 3DS-IC Committee

Since its formation at SEMICON West in July 2011, the Taiwan 3DS-IC has held two committee meetings thus far to continue its discussions on testing and middle-end process.  At the last Taiwan 3DS-IC committee meeting, held October 26, 2011, the committee approved the formation of the 3DS-IC Testing Task Force.  The task force was chartered to develop standards, guidelines, and/or specifications for electrical testing related activities used in 3DS-IC manufacturing for the ultimate goal of yield enhancement.  Activities related to electrical testing of prebond and bonded wafers/devices include, but not limited to:

  • Design for Test (DfT) such as test structures and placement;
  • Test methodologies such as contact method and test procedures;
  • Test fixtures such as probe card and probe interfaces, and
  • Data mining test results

The committee is still evaluating possible standardization activities related to the middle-end process at this time.  The committee intends to focus on processes involving shared activities between wafer foundry and OSATs, including embedded via protrusion and viaed wafer thinning.  This activity would also define outgoing and incoming inspection items and metrologies for intermediate viaed wafers, in-process ESD criteria, in-process inspection items and metrologies in viaed wafer thinning process.

The next meeting for the Taiwan 3DS-IC committee is scheduled for January 5, 2012 and will be hosted by ITRI in Hsinchu.

SEMI Standards Watch, December 2011