3D-IC: Ushering in a New Era in the Semiconductor Industry
25 Executives Share Technology Insights at the SiP Global Summit
Semiconductor packaging technology has transformed from 2D into 3D stacking. Currently, the industry is working on materials, equipment, manufacturing and product standardization to achieve technology optimization, time-to-market expedition and cost reduction. Twenty-five industry executives shared their viewpoints at the “SiP Global Summit” held by SEMI in Taiwan. The three-day event attracted around 1,060 attendees from the industry.
During the 3D-IC Technology session, Sony’s senior vice president Teiji Yutaka demonstrated the newest 3D applications such as floating image projection, wearable 3D displays, action trackers and desktop 3D displays that allow an exhilarating user experience. He pointed out that the semiconductor industry must respond to these trends and develop high-performance products to accommodate these applications.
Chen-Hua Yu, senior director of advanced module technology development at TSMC, stated that the industry’s focus has shifted from chip minimization to micro-integration on the system level to accommodate consumer electronics with low-power consumption, high performance, advanced functions, small sizes and minimized production cost. At this stage, TSV is the most favored systems integration solution, although challenges remain over wafer thinning and interoperability, he said.
Powertech Technology chief executive Scott Jewler called 3D-IC the right technology choice in the midst of demands for new applications. He said 3D-IC is no “fairy tale” as mass production of the chips is already in the offing. However, to reach the goal, an upgrade of technology and equipment is required. Elpida TSV packaging vice president Takayuki Watanabe cited various innovative solutions that reduce power consumption for several new applications.
Victor Peng, senior vice president of Xilinx, said that by using FPGA slice, silicon interposer and TSV technologies, combined with serial arrangement, one can achieve interconnection on the nanometer-level and see design cost significantly lowered.
Hitachi Chemical chief executive Itsuo Watanabe spoke from a materials perspective, saying the right materials for making 3D-ICs can be found by analyzing their temperature, heat resistance and adhesiveness. Reliability and efficiency of the materials will play a critical role in 3D packaging.
Speaking on standardization, IMEC scientific director Eric Beyne pointed out that as 3D-TSV stacking becomes mature and ready to enter commercialization, its impact will be felt across the supply chain, giving rise to the need for standardization. As for the scope of standardization, Beyne said besides TSV production, which already follows a set of standards on future development and efficiency optimization, standardization needs to be extended into the following: wafer thinning, microbumps arrangement, materials selection, interconnection of components, extension of 2D testing architecture, and 3D testing.
3D-IC Test: Supply Chain Collaboration for Developing Cost Effective Solutions
The increasing 3D-IC design and mechanical package complexity will lead to a significant manufacturing test challenge. It is crucial for the entire supply chain— from material suppliers, design houses, test equipment suppliers, package and testing houses— to partner and come out with cost-effective test methodologies and strategies to make these innovations move to commercialization as quickly as possible.
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Demand for bandwidth stimulated by mobile communication resulted in the focus on Wide-IO Memory. In the 3D-IC Test session, Amer Cassier, senior product engineer at Qualcomm, highlighted the advantages of TSV in the manufacturing process and how to improve yield rate by the implementation of innovative KGD (Known Good Die) solution. He pointed out that setting up a parameter data management system is beneficial for consensus tracking of the manufacturing process. To detect bugs and optimize the manufacturing process, the design proposition should include testing, mass production, detection and thermal stress, as well as data mining and statistical analysis.
Roger Hwang, director of ASE Group, highlighted that 3D-IC revolutionized the process of packaging, and that a successful 3D-IC test is closely related to the quality of product as well as cost control. In terms of wafer testing, both assembly house and OSAT must be equipped with in-depth knowledge of materials texture which will be helpful to optimize the testing process. With that, an optimized process can be generated. An excellent cost effective strategy can emerge under the proposition that IC design houses, foundries, testing house in the eco system have collaborated seamlessly.
Talking about the cost-effective solution for 3D-IC test, Sam Ko, deputy director of KYEC, shared similar points of view with ASE. The industry has gained essential momentum in 2D-IC, integrating all the systems in a single chip, and now is marching forward to 3D-IC in every aspect— including dies, foundries, heterogeneous functions, even various form factors, vendors, and IC designers. The evolving dimensions of 3D-IC are diversified and complex, and everyone in the supply chain is totally engaged in the testing process to achieve the goal of reducing costs. Design engineers present DFT principles as well as standard IC interface for each die stack, paving the way to reduce cost.
From the equipment point of view, Benjamin N. Eldridge, senior VP, R&D and CTO of FormFactor, pointed out that there were plenty of heterogeneous function layers involved in the TSV testing process. With standard testing socket solutions, errors and bugs can be detected early in the process of wafer thinning and die stacking. To determine that the final device is operating normally, die and stack detection should be finished before package.
“High-end control for equipment, completed embedded auto test strategy, recover algorithm and simulated end-application are the key factors for heterogeneous integration achieving KGD level,” said Greg Smith, general manager of the Semiconductor Test Division at Teradyne. “Towerless Prober Docking is one of the solutions to secure signal accuracy, equipment cost down, and better flatness of plate interface.”
Embedded Substrate: Integration and Materials are the Key Success Factors
Heterogeneous integration sometimes takes the spotlight in the packaging industry. At the embedded substrate session, Takayosi Katahira, specialist in PWB & Packaging Technology, Devices R&D, at Nokia Corporation, said that mobile devices are getting wider screens and high-processing capability to enable innovative user experience— resulting in tougher requirements for both power supply and compact form factor. As such, PCB board has to be presented in compact layout to contain more devices, not to mention the efficiency requirement on processor, memory and bandwidth.
Bruce Su, VP, ASE Group, said that the testing industry has encountered challenges in wire bonding, flip chip and embedded chip plant. There are still aspects that need to be improved, such as the limitation of IO, thinning die, material matching, accuracy of die connection and accuracy of substrate space. Integrated assembly and bounding technology will be further extended to embedded substrate in the near future.
E. Jan Vardaman, president and founder of TechSearch International indicated that “The dynamic market demand such as request for smaller form factor, diverse features, lower voltage, higher electronic current, increased frequency, higher reliability and lower cost, all drive the technology development of the industry, including the responsive change of layout in embedded substrate. Whether active or passive components, resistor or capacitor, there are both advantages and drawbacks, as such, full comprehension and evaluation of those devices are a must.” Hitachi Chemical further highlighted that the first priority to realize embedded substrate is to provide various advanced properties, with that comes the real practice of high-thermal conductivity, low CTE, high-density technique.
About SiP Global Summit
Given the growing importance of packaging and testing in the global semiconductor supply chain, SEMI held its first-ever SiP Global Summit from September 7 to 9, 2011 under the auspices of SEMI’s Taiwan Packaging and Testing Committee as well as major international enterprises and research organizations
The SEMI Taiwan Packaging and Testing Committee is currently led by Ho-Ming Tong, chief R&D officer and general manager of ASE Group, who was elected to the SEMI International Board and as chairman of the Taiwan Regional Advisory Board in July 2011. Tong is also committed to 3D-IC standards development.
For more information, visit: www.sipglobalsummit.org
November 8, 2011