Transitions on the Horizon Drive Need for Continued Industry Collaboration
Transitions on the Horizon Drive Need for Continued Industry Collaboration
By Brian Trafas, Ph.D., chief marketing officer, KLA-Tencor, Inc.
As we move toward 2012, there remain several critical transitions facing the industry. In today’s consumer driven market, the growing demand for products that are smaller, faster, and cheaper is an unavoidable reality. From tablets and cell phones to mobile PCs and gaming, consumers’ insatiable demand for interoperable, feature-rich, portable devices has reached an all-time high. In fact, the mobile tablet market alone is expected to experience robust growth increasing from 60 million units in 2011 to more than 275.3 million units by 2015.*
With the evolution of the tablet comes more willingness from employers around the world to deploy these types of mobile devices across the enterprise, thereby enhancing the proliferation of these products. Aside from the growth of mobile devices, the increased adoption of cloud computing or rather, cloud-based products, is also revolutionizing how, when and where we access information, further driving the need for smart, Web enabled-devices.
In order to manufacture devices that are smaller, faster and cheaper— meeting consumers’ growing requirements and those brought on by emerging trends, the semiconductor industry is currently experiencing a number of transitions. The commercialization of extreme-ultraviolet lithography (EUV), the exploration and usage of new materials in the semiconductor manufacturing process, the introduction of new design structures, the move to 450mm wafer production and a continued shift towards a foundry-based model are the most important.
To keep pace with Moore’s Law— the concept that the number of transistors that can be placed inexpensively on an IC doubles every two years— the semiconductor industry continues to innovate. Just as there was a strong pursuit to migrate from the 4X/3X nm nodes, the focus is now on the challenge of moving to the 2X/1X nm nodes. Several have commented about the industry approaching the end of Moore’s Law. With several transitions already in progress and innovation at all-time high, it’s unlikely Moore’s Law will end anytime soon. The real challenge is keeping pace with it by innovating new techniques to reach the 2X/1X nm nodes. In fact, it’s really about innovating plus scaling.
The first most widely debated transition the industry is facing is the move from deep ultraviolet lithography (DUV) to extreme ultraviolet lithography (EUV). Industry players continue to make a tremendous investment to develop a next generation technology that will scale devices to smaller dimensions. In retrospect, the industry has been very collaborative— extending 193 nm immersion to multiple generations of devices. As industry leaders continue to work towards the goal of printing smaller dimensions in a cost-effective way, lithography extensions such as double-patterning and EUV will be critical in making 1X nm node a reality. As industry leaders push towards ramping EUV to meet high-volume manufacturing requirements, innovations around source, mask and resist will need to provide the levers for making EUV successful.
In addition to transitions in advanced lithography, there is a host of new materials being introduced at leading-edge design nodes that are critical for extending the functionality of processors. From 2000 to 2004 the industry transitioned from aluminum to cooper to serve as conductors for the wiring on devices. At 4xnm, creative transistor engineering— including stress strain, device structures with metal gates and very sophisticated multi-film stacks were implemented to address leakage and performance issues. The hafnium-based high-k dielectrics are deposited in extremely thin films on the order of 10 angstroms, making this a very delicate and complicated process. In addition, the thickness and composition of materials are critical to the performance of the gate. The continued introduction of new materials plays a critical role in reducing source-drain leakage power, thereby enabling more energy efficient microprocessors. Furthermore, with the help of equivalent scaling we can better enable scaled integrated circuits by using new materials, new process technologies and new device structures.
In addition to new materials and changes in device structures, transistor designs are also playing a pivotal role in device scaling. Within this area the biggest transition is the move from 2D to 3D transistor designs for microprocessors. Particularly for logic devices, we’re witnessing a moving towards fin field-effect transistors (FinFET), a 3-D transistor design that uses a raised fin that requires a smaller footprint and allows for more transistors on a chip. The design also reduces power consumption and yields better batter life on devices. In the memory sector, manufacturers are transitioning to 3D by stacking multiple chips, which is particularly common for NAND devices.
Along with the 3D device structures, the industry is moving to 3D integrated circuits and packaging by stacking silicon wafers and/or dies and interconnecting them vertically through the use of a through-silicon Via (TSV) process. For example, a customer might create a single chip package consisting of a DRAM and CMOS chip. By using this technology, manufacturers can pack a great deal of functionality into a small footprint thus meeting the form factor required for today’s consumer. The TSV process is very complex as each of the TSV’s must be precisely developed, plated and filled completely with metals and not impacted by the stresses involved during high temperature thermal processing and extensive back grinding steps. If one fails, the entire device does not work.
While the industry navigates advances in lithography, new materials and devices structures, chipmakers are showing strong indications of advancing the transition to 450mm wafer sizes—the next wafer size anticipated to drive down the cost of consumer products. Signs include Intel’s recent announcement that its D1X facility slated to open in 2013 will be 450mm compatible; TSMC’s acknowledgement that a 450mm pilot line could be seen by 2013 or 2014; and the introductions of several 450mm equipment tools during SEMICON West in July 2011. Furthering the move, IMEC and ISMI already have well-established programs in place focused on manufacturing challenges involving 450mm wafers. With a wafer transition, historically, every eight to 10 years, there’s a high likelihood that the industry will transition to 450mm with the goal of reducing manufacturing costs.
When these significant changes are coupled with consumer’s influence on the semiconductor industry, it is critical that semiconductor companies ramp and yield these processes as quickly and efficiently as possible. To yield smaller device structures, every critical parameter needs to be measured and more tightly controlled: CD and profile uniformity, overlay error and defectivity have a tremendous impact on yield and device performance. Each one of the challenges mentioned earlier create tremendous yield and process control hurdles.
For semiconductor companies, achieving yield goals is not the only important factor; it is also critical how quickly they can reach these goals. This is due to the large influence that the consumer market has on the semiconductor industry. Consumers want products quickly, at a low cost and with a longer battery life, so if a yield ramp is off by even a few months or a fab suffers an unexpected yield loss, semiconductor manufacturers can lose many hundreds of millions of dollars in current or future business. In order to achieve the best yield ramps at the lowest costs, fabs implement complex process control strategies to help them identify and solve yield issues as quickly as possible while maintaining the lowest overall costs.
Lastly, one cannot overlook the industry shift towards a foundry-based model. Instead of designing and manufacturing chips, more companies are focusing solely on designing chips in a move to avoid the astronomical R&D costs associated with manufacturing. As the industry pushes to the foundry model, it improves efficiencies. It’s anticipated that this trend will continue to help lower costs and increase yields. As a result, this transition has led to more industry consolidation. Where once there were 20 plus companies capable of manufacturing leading-edge devices, now there are approximately 10. In the future, it’s likely this number will continue to shrink further.
With all these transitions on the horizon, tighter industry collaboration is essential. Industry players are and will continue to pool resources and budgets to address complex issues, ensuring the viability of all companies in the space. Already this is evidenced by the advent and criticality of industry consortia and organizations such as IMEC, LETI, International SEMATECH, SELETE, and Albany Nanotech.
About the Author
Brian Trafas, Ph.D., serves as the chief marketing officer at KLA-Tencor, Inc., where he is responsible for defining product requirements for the company’s products serving the wafer, mask, IC, data storage, solar and LED markets. With two decades of experience in the semiconductor capital equipment industry with an emphasis on process control, Trafas is a sought-after author having written more than 30 technical papers. He has written extensively about CD process control, advanced patterned wafer inspection methodologies and the application of scanning probe microscopes. Additionally, he has earned several industry honors including the R&D 100 Award from R&D Magazine.
September 7, 2011
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