3D-IC Opens a New Era of IC Packaging and Testing
ITRI’s Industrial Economics and Knowledge Center recently forecasted that the production value of 3D-ICs for mobile phone applications will hit US$ 3.65 billion by 2015. With the growing popularity of smart phones, e-book readers and other mobile devices, manufacturers have placed a stronger focus on heterogeneous integration through System-in-Package (SiP) to enhance user experience.
Topology Research Institute, meanwhile, has pointed out that 3D-ICs will be the mainstream in the post-PC era, a point validated by Powertech, Elpida and United Microelectronics Corp., which recently joined forces to develop 3D-ICs targeting below-28-nm process nodes, with trial production scheduled for the third quarter. Other packaging and testing houses such as ASE and SPIL are also focusing on 3D stacked packaging. Indeed, IC firms are bracing themselves for the “Era of 3D-ICs.”
Just as PlayStation 3 is taking game consoles into the world of 3D, so will the packaging technology transition from 2D to 3D. Operators are looking to strike a balance between performance optimization, time-to-market expedition and cost reduction through the use of different materials, equipment, process nodes, and product standardization and commercialization methods.
In the process of 3D-IC commercialization, many packaging and testing challenges need to be overcome to help manufacturers achieve the anticipated yield rates. Dr. Ho-Ming Tong, general manager and chief R&D officer of ASE, noted: “Despite progress in 3D-IC development over the past years, challenges remain in the areas of cost control, design, mass production and testing in the lead-up to commercialization. Given the silicon interposer-based 2.5D-IC technology has become mature, its deployment will expedite migration from the 40-nm node to 28-nm. With computing and smart devices fueling growth of the market, commercialization of 2.5D and 3D-ICs may take place in 2013.”
Terry Tsao, President of SEMI Southeast Asia, said: “3D-IC production is a trend facing semiconductor testing and packaging operators, which are striving for mass production and are looking for more cost-effective solutions to overcome current technology bottlenecks. SEMI will be happy to help Taiwan manufacturers achieve further successes in this arena.”
SiP Global Summit 2011
SEMI will hold the first-ever SiP Global Summit from September 7-9. The three-day SiP Global Summit will consist of three major forums— namely 3D-IC Test, 3D-IC Technology and Embedded Substrates— with representatives from 25 of the world’s top-notch IT firms slated to share insights into the 3D-IC, TSV, silicon interposer and embedded substrate technologies. Participants in the summit will include ASE, Elpida, Formfactor, KYEC, Nokia, Qualcomm, Powertech Technology, Sony, SPIL, TSMC, Verigy; and R&D and market research organizations including Gartner, IEEE, IMEC, Yole Development and Industrial Technology Research Institute (ITRI). Free registration for the event is available at www.semicontaiwan.org/sip2011
SEMICON Taiwan Advanced Packaging/Testing Gallery
SEMICON Taiwan will hold the SiP Global Summit simultaneously, and will feature the Advanced Packaging/Testing Gallery (sponsored by ASE and KYEC). The pavilion will delight with cutting-edge testing/packaging technologies and applications. Both the SiP Global Summit and SEMICON Taiwan are now open for registration at www.semicontaiwan.org/sip2011 free of charge.
August 2, 2011