Transistor Evolution Drives Wide-Ranging Research
By Balaji Chandrasekaran, Applied Materials, Inc.
Classic transistor scaling has given way to modern scaling and related performance enhancement based on new materials in strain engineering and high-κ metal gate schemes. For the 22nm node and beyond, devices will incorporate three-dimensional (3D) transistor architectures and an even wider range of new materials to sustain Moore’s Law, posing challenges that are driving wide-ranging research on new process capabilities for transistor fabrication.
The 3D FinFET (Fin Field Effect Transistor) transistor is a new architecture that substantially reduces power use while enabling advanced transistor scaling. A critical process step is recessing the STI oxide to form the “fin.” Standard wet etching, dry plasma etching, or plasma-free dry oxide removal processes can be employed. The latter iterates between growth and sublimation of ammonium fluorosilicate, consuming a well-controlled amount of oxide. Recent research on forming a FinFET structure using this process showed good electrical results for Ion vs. Ioff performance relative to planar transistors.
Much recent research has focused on new channel materials, among which III-V and Ge materials are front runners, given their adoption in optoelectronic and communication devices and in logic devices. In theory, such III-V materials as InSb or InAs offer 50-100 times the electron mobility of silicon, and Ge provides higher hole mobility than silicon, making them attractive candidates for NMOS and PMOS, respectively. A possible architectural construct for implementing these new channel materials is a Quantum Well Field Effect Transistor (QWFET) derived from a high electron mobility transistor device in which the active channel layer is sandwiched between two other materials and carriers are confined to the active layer (hence quantum well). In the future, III-V and Ge channel-based transistors will be incorporated into 3D architectures, whose feasibility with silicon has already been demonstrated.
The introduction of the High-κ Metal Gate (HKMG) has been a key inflection in addressing effective oxide thickness and enabling continued scaling, and has placed heightened demands on interface engineering. Precise uniformity control and freedom from contamination or exposure to air throughout the deposition, nitridation, anneal sequence are required in forming the high-κ/SiON/Si interfaces, suggesting that integrating these steps on a single platform will become essential for good yields. Future effective oxide thickness scaling approaches are likely to include increasing the κ value of the high-κ dielectric, reducing the interface layer (IL) thickness, or increasing the IL κ value. Reliability will be a key factor influencing adoption. For the metal gate electrode, integrated processing also offers the best conditions for compositional and contamination control while depositing multiple metal layers. In addition, highly conformal atomic layer deposition (ALD) or chemical vapor deposition will be widely used to overcome sheet resistivity and metal fill challenges as critical dimensions shrink. ALD in particular is likely to be widely adopted as HKMG stacks become integrated onto 3D architectures, necessitating exceptional conformality along all surfaces.
In planar transistors, source/drain (S/D) parasitic resistance control and ultra-shallow junction formation are key concerns. In-situ dopant incorporation during epitaxial growth and dopant activation to the fullest extent are critical in lowering resistance of the S/D region (RSD) and its extension region (RSDE). Also, rapid thermal anneal processes must maintain an ultra-shallow junction depth within a lower thermal budget, necessitating lower anneal temperatures and shorter residence times. With the advent of 3D FinFET transistors, S/D regions may be grown by selective epitaxy on top of the silicon fins. Uniform doping across the 3D surfaces of the fins—essential for device performance—will make conformal doping technologies imperative.
In fully depleted silicon-on-insulator (FDSOI), one of the new substrates designed for lower operating power and better performance, the already thin extension regions can undergo amorphization damage during ion implantation, which degrades RSDE, and a dopant loss path to buried oxide can worsen RSD. Recent studies employing a diffusion-based approach to drive dopants from a faceted p+ epi S/D into the extension regions show a much lower parasitic resistance for PMOSFETs.
Sheet resistivity and interface resistance are the main concerns in contact scaling. Sheet resistivity increases geometrically at smaller dimensions. Using large rectilinear trench contacts in lieu of small circular plugs relieves this problem. Interface resistance can be reduced through new materials engineering. Nickel silicide and NiPtSi have the lowest bulk resistivity among common silicides. Continued junction scaling, however, calls for a thinner silicide layer. Uniform conversion to the low resistance monosilicide phase, avoiding the resistive NiSi2 phase, is vital. This can be achieved by using an optimized physical vapor deposition process to ensure uniform metal deposition with density and topology, a dry chemistry pre-clean process, and advanced anneal steps to obtain the best possible uniformity at the lowest thermal budget. Two related advances are backside rapid thermal annealing to improve uniformity in the conversion step and laser millisecond anneal, which reduces nickel diffusion. In the future, one can expect thinner barrier materials, advanced laser anneal technologies, and new metal choices (e.g., low resistivity tungsten or copper). Integration with 3D FinFET transistors will likely build upon the rectilinear trench contacts, with multiple fins potentially sharing common contacts.
Strain engineering has played a key role in perpetuating Moore’s Law. Two commonly employed strain approaches are dual stress liners and raised or recessed S/D structures. Si-Ge structures have been implemented for PMOS transistor S/D regions to transfer compressive strain to the channel and increase hole mobility. Similarly, Si-C structures are considered potential candidates for NMOS S/D regions; research has shown more than 50% higher electron mobility. Scaling for greater strain to achieve higher drive currents in future can be achieved through higher dopant concentrations, greater geometrical depth, and channel proximity of S/D regions. Integrating strain engineering into FinFET transistors will be an inevitable yet highly challenging extension of this technology.
Transistor scaling into the next decade will be enabled by new architectures and materials. New architectural constructs, such as 3D FinFET, QWFET, and FDSOI will increase process complexity and require innovative and holistic solutions.
Balaji Chandrasekaran is a strategic marketing manager in the Silicon Systems Group at Applied Materials, Inc.
August 2, 2011