IC Packaging Innovation Increasingly Replacing Moore’s Law in Mobile Electronics Competition

IC Packaging Innovation Increasingly Replacing Moore’s Law in Mobile Electronics Competition

Smart phones, tablets, e-readers and other mobile applications are increasingly replacing PCs as the key drivers of the semiconductor industry. Consequently, IC packaging innovations that deliver high performance applications in a low-profile, low-cost, and low-power design are competing with next node processing technologies as the critical platform for competition in the mobile segment.  OEMs, system developers, foundries, packaging and test subcontractors, chip manufacturers, and fabless chip companies are placing high-risk, high-stakes bets on next-generation packaging solutions that are more able to deliver “faster, better, cheaper”  results than advances in wafer processing.

Many companies will discuss their views of the increasing complex and varied IC packaging options at SEMICON West 2011 on July 12-14 in San Francisco. The July 12 Opening Keynote features Tien Wu, chief operating officer of ASE, who will present “The New Dynamics of the Semiconductor Business,” kicking off the three-day exposition and conference. 

Mobile devices are being transformed by MEMS sensors and devices that leverage advanced packaging technologies and require tight integration with ICs.  Session chair, Prof. Dr. Klaus-Dieter Lang, Head of Fraunhofer IZM, will lead the session, “Heterogeneous Integration with MEMS and Sensors” (Tuesday, July 12 from 2:00pm-4:00pm at the NorthOne TechXPOT). This session explores leading integration technologies and strategies in MEMS featuring speakers from Microsoft, TechSearch International, Fraunhofer IZM, Toshiba, CEA-Leti, Infineon Technologies, Silex Microsystems, NIST, and Analog Devices.

The most dramatic developments in IC packaging concern 3D integrated circuits that propose to stack dies and connect through TSVs to deliver improved functionality, power consumption, space efficiency, and bandwidth. The drive for 3D has spawned a whole ecosystem for TSV technologies from industry, academia and research institutes, to equipment and material suppliers. Silicon interposer (2.5D) technology based upon TSV has become an important technology in this first wave of 3D implementation, but without design standards, test platforms, and roadmaps that link the strategies of memory, MPU, GPU and other chip manufacturers—including foundries and packaging firms— to a common, achievable vision, the benefits of 3D IC could be illusive.

Critical issues in 3D-IC will be discussed in the open session, “3D in the Deep Submicron Era” (1:30-5:00pm at the NorthOne TechXPOT stage) on Wednesday, July 13.  Hosted by session chairs, Jie Xue, director, Technology & Quality, Cisco Systems and Gamal Rafai-Ahmed, AMD fellow, AMD, the session will feature speakers from Xilinx, SEMATECH, ITRI, Georgia Institute of Technology, Amkor Technology, GLOBALFOUNDRIES, Avago Technologies, Mentor Graphics, Yole Developpment, Renesas, IBM, ASE, imec, Applied Materials, and Qualcomm.

While much has been written about emerging packaging and integration technologies like 3D TSV, a majority of today’s IC market is optimizing and migrating to advanced packaging technologies such as copper wire bonding, cu pillar flip chip, fan-out wafer level packaging, and other proven solutions.  Current trends and developments in these areas will be explored in the session, “Contemporary Packaging: Challenges and Solutions for 40nm and Beyond” (Wednesday, July 13 from 10:30am-12:30pm at the NorthTwo TechXPOT).  Led by session chairs, Tom Gregorich of MediaTek and Rich Rice of ASE, this session features presentations and panel discussions with representatives from Gartner, GLOBALFOUNDRIES, TSMC, Siliconware Precision Industries (SPIL), Atmel, and STATS ChipPAC.

Also on Wednesday, July 13, the ITRS Summer Public Conference takes place from 7:30am-2:00pm at the San Francisco Marriott Marquis. The IMAPS Workshop on Advanced Interconnect Technologies also takes place from 12:30-5:30pm at the SF Marriott Marquis. On Thursday, July 14, the IMAPS Workshop on Wire Bonding takes place from 7:00am-5:30pm at the Marriott Marquis.

More information on packaging technology and trends sessions at SEMICON West is available at http://www.semiconwest.org/Segments/Packaging. To learn more about SEMICON West, visit: www.semiconwest.org.

July 5, 2011