3D-IC Stacked Integrated Circuit Innovations Ready for Prime Time Manufacturing

3D-IC Stacked Integrated Circuit Innovations Ready for Prime Time Manufacturing

For Learning about the Changes Occurring in the Field, IEEE/SEMI ASMC Offers Best Venue

By Paul Werbaneth, MEMS Investor Journal

 Why is 3D-IC technology in the news so much lately? Perhaps because the commercial version of 3D-IC technology contains the essence of so much new development work in both chip fabrication and in chip packaging…and because 3D-IC technology has the ability to make the next generation of tablet computers even slimmer, new smartphones even more cool, and hand-held video gaming units even sportier.

But just what is a 3D Stacked Integrated Circuit (3D-IC), and how do you recognize one when you see it?

Dr. Philip Garrou, writing in November 2007, offered this definition:  As I’ve stated in a number of places the easiest way to spot 3D-IC integration is to look for three things: (1) thinning; (2) bonding; (3) through silicon (or other semiconductor) vias.  Some of the packaging folks from IBM are now saying that mounting a chip on a silicon substrate is ’3D Integration.’  Again, any stacking, by definition is 3D, but if their definition is true, then mounting a through hole component on a PWB is 3D integration also!  Let’s keep the definitions realistic guys — 3D-IC integration has TSV.”

 From 2007 to 2011, three-dimensional technologies for IC fabrication have moved from “lab to fab,” — now right on the verge of high-volume commercial manufacturing, thanks to dedicated efforts and hard work on many fronts, including that of SEMI.

James Jian-Qiang Lu (IEEE Fellow and Associate Professor, Rensselaer Polytechnic Institute) says this about the current state of 3D Stacked-IC integration in semiconductor fabrication:  “While 3D processing technologies and equipment will be further developed for Through Silicon Via (TSV) applications, for example in wafer bonding, alignment and thinning process technologies, 3D-IC device integration in general is close to ‘prime time’ for volume commercial manufacturing.” 

Lu adds, “There are still some entry cost burdens pending for 3D-IC technologies, including additional investments in the TSV process module infrastructure, ECAD, standards, and general business readiness, but I expect 3D-IC applications will continue to advance in the coming years in an evolutionary fashion, instead of advancing in a revolutionary fashion, as will EUV lithography, 450mm diameter wafers, and the other significant changes we can anticipate seeing in future CMOS IC device fabrication.”

Klaus Hummler (3D Integration manager at SEMATECH) concurs:  “Front side processing technologies for 3DS-IC in SEMATECH’s via middle approach have matured quite nicely over recent years, with reasonable incremental development costs.  We are focusing our efforts now on wafer backside processing steps for 3DS-IC, the mechanical handling of bonded wafers, and on packaging integration, especially high-throughput direct copper bonding.”

Responding to the need for standards in 3DS-IC fabrication, SEMATECH launched a new 3D Enablement program in December 2010 to drive industry standardization efforts and technical specifications for heterogeneous 3D integration.

Andrew Rudack (SEMATECH, 3D Standards and Metrology) says “SEMATECH is taking a leadership role in the discussion and promotion of standards for 3DS-IC technology.  We are identifying needs and, working together with SEMI, we are assembling committees and task forces in response to the input from our members and from our own significant experience to date with hands-on processing of Bonded Wafer Stacks (BWS) for 3D-IC fabrication.  Our goal is to leverage standards to head-off potential show-stoppers.”

Further information on SEMI’s activities in 3DS-IC manufacturing standards comes via James Amano (director, SEMI International Standards) who says “The SEMI 3DS-IC Committee was created in late 2010, and has several activities underway in three task forces. The Inspection and Metrology Task Force is measuring the properties of TSVs, the Bonded Wafer Task Force is working on parameters for bonded wafer stacks, and the Thin Wafer Handling Task Force is developing standards for transport and storage.  In addition, a new task force to address trimming of device wafers and carrier wafer dimensions is expected to start work at the 3DS-IC Committee’s next meeting on Tuesday, July 12, 2011 at SEMICON West 2011.  The committee is currently chaired by Applied Materials, Qualcomm, Semilab, and SEMATECH.”

3D-IC Integration at the Core of Upcoming IEEE/SEMI ASMC

3D-IC innovations as a ready-for-prime-time manufacturing topic are at the very core of the 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

Rudack says:  “We will present a detailed example of BWS hands-on learning in our upcoming IEEE/SEMI ASMC 2011 paper, in which we evaluate the need to slow down robot handling for bonded wafer stacks.  We observed BWSs slipping on robot end effectors, potentially creating mechanical displacement and wafer misalignment, an issue that could hinder the commercial adoption of 3DS-IC technologies.  And we want to make sure that doesn’t happen.”

The IEEE/SEMI ASMC is the annual “go-to” forum showcasing the global chip industry’s best known methods for creating and managing efficient, high-payoff technical collaborations between device makers, tool vendors, and academia, for implementing factory productivity enhancements and cycle-time improvements in 24/7 fab lines, and for ratcheting device and line yields up to their highest obtainable levels for both legacy and for leading-edge semiconductor device wafers.

The 22nd Annual ASMC, ASMC 2011, will be held May 16-18, 2011 at the Saratoga Hilton Hotel in Saratoga Springs, New York, an historic town in New York State’s Capital Region.  Nearby attractions include: The College of Nanoscale Science and Engineering (Albany NanoTech), GLOBALFOUNDRIES’ newest 300mm production wafer fab, Rensselaer Polytechnic Institute, SEMATECH, and the fresh spring waters from which Saratoga takes its name.

Taking as a theme “Collaboration Across the Semiconductor Manufacturing and Development Global Supply Chain,” the ASMC 2011 Conference co-chairs, Holly Magoon (Nikon Precision) and Scott Lantz (Intel Corporation), together with the ASMC 2011 Committee, have created a dynamic program featuring these highlights:

  • Keynotes by Norm Armour (VP and GM, Fab 8, GLOBALFOUNDRIES) on “From Contract to Collaboration: Delivering a New Approach to Semiconductor Manufacturing”, Dr. Gary Patton (VP, Semiconductor Research & Development Center, IBM Systems & Technology Group) on “Semiconductor Technology: Trends, Challenges, & Opportunities”, and Peter Wright (director of Research, Tradition Equities) on “A Capital Markets View on Manufacturing: Opportunities & Challenges for 22nm and Beyond”
  • Tutorials by Prof. James Lu (RPI) on 3D-IC and Obert Wood (principal member of Technical Staff, Strategic Lithography Technology Department, GLOBALFOUNDRIES) on EUV
  • A Panel Discussion on “Models for Successful Partnerships in Semiconductor Manufacturing,” led by David Lammers (editor-in-chief, SemiMD), with contributions from Dr. Walid Ali (Advanced Technology Investment Company (ATIC)), Olivier Demolliens (CEA-Leti), Michael M. Fancher (College of Nanoscale Science & Engineering), and Ari Komeran (Intel Corporation).
  • Technical Sessions focused on Factory Optimization, Advanced Metrology, Process Development and Control, Advanced Lithography, and Yield Optimization.
  • Collaboratively co-authored Technical Presentations such as “Ambient Persuasion in the Factory: The Case of the Operator Guide,” “On the Technology and Ecosystem of 3D / TSV Manufacturing,” and “Optimization of Pitch-Split Double-Patterning Photoresist for Applications at16 nm Node.”

And there’s more:  An opportunity to tour the GLOBALFOUNDRIES Fab 8 Luther Forest site, followed by a reception at Saratoga Springs’ historic Canfield Casino; in-depth interaction with ASMC 2011 authors and attendees at the ASMC interactive poster session and reception; and the International SEMATECH Manufacturing Initiative (ISMI) session co-located this year with ASMC, with presentations on Manufacturing Sustainability, Prognostic and Health Management Practices Applied to Semi Manufacturing, Cycle Time, 450 mm, and (that term again) Collaboration.

ASMC 2011 is generously sponsored by Applied Materials, Edwards Vacuum, KLA- Tencor, Matheson, Metryx, Nikon, NY Nanotech, Saratoga Convention and Visitors Bureau, the Saratoga Economic Development Corporation, and Synopsys.  Co-sponsors are CPMT, EDS, and IEEE, with Entegris, and ISMI, providing additional support.

The IEEE/SEMI Advanced Semiconductor Manufacturing Conference proceedings form the strong center of many a wafer fab engineer’s technical reference library, and selected papers from ASMC are routinely published in the IEEE Transactions on Semiconductor Manufacturing.  The 3D-IC fabrication papers and tutorial, as discussed this year at ASMC 2011, will surely become part of the future canon, as have so many other seminal talks from ASMC in years past.

“Projecting forward, ASMC 2020 is likely to be a completely 3D-IC conference,” according to Andy Rudack.  “At the rate ASMC has been adding 3D papers and tutorials, it seems inevitable.”

For more information on the Advanced Semiconductor Manufacturing Conference (ASMC), please click here.


May 3, 2011