Session 7: FPE Manufacturing Facilities
Prototyping of Printed TFTs on Pilot Line for Smart Surface Application
Wednesday, June 21, 2017
9:05 AM - 9:25 AM
This paper will introduce the methodologies and recent results developed at CEA-LITEN for the scale-up of printed TFTs circuits for flexible sensor systems. The paper will introduce the ecosystem of printed devices developed on PICTIC Pilot Line (GEN1 format) and the 4 prototyping platform set-up for TFT device optimization, circuit design, process scale-up and reliability. The papers will focus on the Process flow developed for Printed OTFTs and scale up of the technology on GEN1 format with gravure printing technics. Statistical performances of polymer based OTFT with mobility ~ 1cm²/V/s will be presented as well as integration in multiplexing circuits and active matrix (50ppi). The downscaling strategy of printing resolution down-to 50 µm workout in collaboration with Material and Tool supplier within ATLASS- Eu Project will be also presented as well as roadmap for mobility/voltage optimization.
Micael CHARBONNEAU (32, Male) graduated as Engineer at Grenoble National Institute of Technology with diploma in digital circuit design & device Engineering and received Ph. D in the Micro-nanotechnology. He worked at the CEA-LETI in the field of silicon microelectronic on Emerging Resistive Memory and joined CEA-LITEN in 2012 for the development of printed memories on plastic and further project for circuit design & system partitioning with embedded interfacing CMOS Circuits & Active Matrix for sensors. Since 2014, he is leading of Printed TFT activity in CEA-LITEN and involved in several national (Carnot, FUI) and EU projects (COSMIC, DOMINO, IFLEXIS,ATLASS) , his activities have been related both to circuits design with academic and industrial partners and to devices development and process prototyping for the scale-up of OTFT technologies on the PICTIC pilot line platform.