Session 18: FHE Chip Integration
Low Temperature flip chip bonding technology applicable to flexible hybrid electronics in the IoT era
Thursday, February 15, 2018
11:20 AM - 11:40 AM
Since its early days of the industry, electronics apparatus has been in a rigid and flat surfaced case. ICs have been soldered on rigid substrate at high bonding temperature. However, in the IoT era, electronics components connect with the variety of applications which require different forms and shapes of outlook which lead substrate and board should be flexible and complex form. Conventional flip chip bonding technology, such as solder bump and copper pillar, need to raise bonding temperature around 260-degree C, eventually does not satisfy this flexile hybrid electronics(FHE) application requirement. We have originally developed flip chip bonding technology which consists of the bump formation by Conductive Paste (CP) printing followed by Non-Conductive Paste (NCP) dispensing and flip chip bonding at temperature as low as 120-degree C. Bumps with silver particle loaded epoxy resin on substrate were formed by screen printing. This enable us to make fine bump formation down to 60um minimum bump pitch and 30um bump diameter with tuning of screen printing process. After the bump formation, NCP dispensing and flip chip bonding at 120-degree C which secure reasonable low electric resistance, 8x1E-4 ohm cm2, and strong adhesion of chip and substrate. The bonding temperature of this technology can be lowered down to 80-degree C without much difficulties, but just by fine tuning of Ag paste and its contents. This momentum will create a lot more of future applications and be one of the core technology in the coming IoT era in FHE.
Specialized in electronic material engineering in Kanazawa University in Japan. After experience in IC fabrication process and semiconductor device development in Sony, he joined CONNECTEC JAPAN, and has been in charge of semiconductor assembly process development.
CONNECTEC Japan Corporation