EUVL: Taking It Down to 5nm

EUVL: Taking It Down to 5nm

by Debra Vogler, SEMI

The semiconductor industry is nothing if not persistent — it’s been working away at developing extreme ultraviolet lithography (EUVL) for many years. Though its production insertion target has slipped over the years, some say that the industry is getting closer to its introduction at the 5nm node. But it’s also true that some may be hedging their bets.

Whatever camp you fall into, the discussion is sure to be lively as a team of experts tackles the status of advanced lithography options that can get the industry from node 10 to node 5 (session “Lithography: Charting a Path, or Paths, between Nodes 10 and 5”, part of the Advanced Manufacturing Forum) at SEMICON West 2016 (July 12, 10:30am-12:30pm). Confirmed speakers for this event include Robert Aitken (ARM), Stephen Renwick (Nikon Research Corporation of America), Ben Rathsack (TEL), Mike Lercel (ASML), Mark Slezak (JSR Micro, Inc.), and Harry Levinson (GLOBALFOUNDRIES). The session will be moderated by Lithoguru’s Chris Mack. SEMI interviewed some of the session speakers to get a preview of the issues most likely to be addressed.

Equipment status

Mike Lercel, director of product marketing at ASML, told SEMI that his company is very confident that EUVL will be ready for next-generation nodes, having demonstrated progress on the NXE:3350B, which is intended for volume production: achieving 1,368 wafers per day at the ASML factory, and excellent imaging and overlay performance at >80W. He further noted that the company’s logic customers will take EUV into production in 2018-2019, so it needs to ship in volume a year before — likewise for DRAM. “We believe that EUV is cost-competitive around 1,500 good wafers per day, but the crossover point may be lower depending on the customer and the application.”

Having already achieved the productivity milestone of 1,368 wafers per day makes EUVL cost-competitive or break-even for many applications, said Lercel, primarily because multiple patterning is becoming too difficult and EUV is needed to reduce this complexity. “Additionally, we’ve exposed more than 300,000 wafers on multiple NXE:3300 scanners at customer sites and that has accelerated our rates of learning. A 125W EUV source setting has been qualified and is ready for field rollout, and we demonstrated 200W source power at ASML.” He also noted that the company has a robust EUVL product roadmap, including a high-NA EUV scanner, which will take it into the next decade and beyond. “As long as the industry continues to scale and we are not close to reaching devices’ physical limits, there will be a need for EUV.”

Lercel acknowledged that EUVL productivity must continue to be improved and throughput is closely connected to source power and tool reliability. “We’ve derived new understandings from plasma modeling and computational lithography that have enabled us to significantly increase our conversion efficiency,” said Lercel. “This was a key contributing factor in our latest 200W achievement and builds confidence in our ability to reach 250W by the end of the year, which is the source power required for 1,500 wafers per day.”

Materials and infrastructure for EUVL

There are still a number of challenges remaining for the infrastructure needed to support EUVL. Among them are actinic inspections for blanks and resists. “Deposition tools and post-pellicle mask inspection must catch up to support EUVL,” said Lercel, who told SEMI that notable progress has already been made on E-beam mask inspection high-volume manufacturing (HVM) tools and on an actinic blank inspection tool development program led by the EUVL Infrastructure Development Center (EIDEC).

In other developments reported by Lercel, Zeiss is working on an AIMS tool for defect disposition; and at imec’s EUV Resist Manufacturing & Qualification Center (EUV RMQC), the industry-wide manufacturing infrastructure and quality control capabilities needed to take EUVL into HVM are being finalized. Other R&D efforts are continuing to improve EUV blank quality process and yield — defects are now reaching single digits said Lercel. ASML is also in the process of commercializing a pellicle. Significant gaps still exist with respect to a blank multi-layer deposition tool that needs to have improved defect results. “Multiple deposition techniques are being evaluated to define the HVM tool approach,” said Lercel. “And post-pellicle mask inspection (APMI) is not on timeline for insertion,” so the industry needs other options.

Regarding EUVL resists, Mark Slezak, executive vice-president, at JSR Micro, Inc., told SEMI that short-term, the materials industry is continuing to evolve and improve chemically amplified systems that are allowing technical requirements to be met at 7nm (see Figure 1 for examples of recent performance data). “Longer term, the industry is focused on new alternative approaches to chemically amplified systems with a variety of techniques, including molecular resists, nano-particles, and advanced sensitizers,” said Slezak, who will also present at SEMICON West 2016. “Additionally, in the case of both 193i and EUV, the material industry is working on post-development solutions, such as chemical shrink, pattern collapse mitigation, and combinations with DSA (directed self-assembly) that enable further imaging extensions.”

Figure 1: Examples of recent progress in patterning materials.
Source: ASML, PSI, and imec

As a company, JSR Micro is preparing to provide scaled-up EUV materials in a HVM setting, including advanced quality control, as early as the end of 2016, Slezak told SEMI. “However, we see that the most likely insertion point for significant volumes is in the 2018 time period.”

Overall outlook

Chris Mack summed up the industry’s current dilemma with respect to EUVL and getting from node 10 to node 5. “The whole idea of continuing on the Moore’s Law progression is to reduce the cost of a transistor by shrinking it,” Mack told SEMI. “We’ve seen a flattening of the cost/transistor trends over time lately, and I think there are some serious questions as to whether or not any specific new technology node from 10nm on will actually result in a lower cost/transistor — and if it doesn’t, there won’t be much motivation for designs to migrate to these nodes.”

Mack further observed that the cost of lithography already accounts for more than 50% of the cost of making a chip, and possibly even as high as 70% depending on the design. “As those costs escalate with each node, we worry that the cost savings won’t be enough to compensate for the higher design costs.” Citing conventional wisdom, Mack noted that the rule-of-thumb with respect to the break-even point for deciding to use EUVL is that it has to be able to cost-effectively replace three 193nm immersion steps (or masks). While there are a lot of assumptions that go into the cost-of-ownership models, Mack explained that if throughput levels can get to around 60-90wph, that would make one EUV layer cost-competitive with three 193nm immersion exposures. “I think most people agree that EUV would then be worthwhile to do. The hope is to be able to do that at the 5nm node.”

Aside from the actual technical challenges that remain to be solved before EUVL can be inserted into HVM, the major hurdle is time. “People are planning the 7nm logic node right now,” said Mack, “and no one is willing to commit to EUV for 7nm because it’s not ready.” He further explained that TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node and then implement EUV in manufacturing at the 5nm node. That would place it at around the 2020 time frame. “If EUV hits its schedule between now and 2018/2019, then we may see TSMC commit to using EUV at 5nm.” Conversely, if the EUV schedule slips and is still too risky to implement, then when 2019 comes around, it could very well be that EUVL will be pushed out even further. “Because foundries have to accept design rules about two years before manufacturing begins, and because the design rules for multiple-patterning 193 immersion are very different from single-patterning EUV, TSMC and other foundries will have to make their call about two years from now.”

For DRAM, Mack says there is still a desire for EUV to be successful, but the window is rapidly disappearing. “We might see more chip stacking as a solution going forward for DRAM,” said Mack, but “then we could see 193nm immersion SADP (single immersion double-patterning) for 20nm DRAM.” Below 20nm DRAM, If EUV isn’t ready, Mack says that chip stacking would be the solution, which leaves EUV for logic, primarily at 5nm.

“Here’s where an interesting phenomenon happens,” Mack told SEMI. “The classic view of Moore’s Law — a doubling of the number of components on a chip every two years — has been carrying on for over 50 years. Current trends are redefining the meaning of Moore’s Law (see Figure 2).”

Figure 2: Moore’s Law trend. Courtesy: Chris Mack

These speakers and more will present at SEMICON West 2016 (July 12-14) in San Francisco, Calif. The new SEMICON West offers eight forums: Extended Supply Chain, Advanced Manufacturing Chain Forum, Advanced Packaging Forum, Test Forum, Sustainable Manufacturing Forum, Silicon Innovation Forum, Flexible Hybrid Electronics Forum, and World of IoT Forum. Register before June 3 and save $50.The industry is seeing a slow-down in, i.e., 3-year cycles instead of 2-year cycles. “If that trend continues and EUV is late, that would give some breathing room for EUV to catch up. So it might be ready in time for the 5nm node.”

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May 24, 2016