Debate about EUVL Still Drives Discussion

Debate about EUVL Still Drives Discussion

by Debra Vogler, SEMI

SEMICON West will again place advanced lithography in the spotlight with a TechXPOT session on the topic (The Economics of Choosing a Lithography Strategy; Thursday, July 13, 10:30am-12:30pm). SEMI interviewed some of the confirmed speakers to tease out the important issues particularly the economic aspects driving decisions. For the complete list of speakers and the agenda, go to

Mike Lercel, director of Strategic Marketing at ASML, told SEMI that there are no infrastructure show stoppers that will impede the introduction of EUVL at the 7nm and 5nm nodes. “Two years ago, we showed a pellicle prototype and technical drawings, and this year we have successfully manufactured pellicles without defects that print,” Lercel told SEMI (see Figure 1). “We also developed the tools for the mask shops that are available to mount and demount pellicles onto EUV reticles, and have shipped multiple tool sets to customers.”

Figure 1

Source: ASML

The company is currently supporting the ramp of the 10nm logic node at chipmakers, as well as process development for the 7nm foundry node with its fourth-generation TWINSCAN NXT:1980 system. ASML expects that the first customer will start volume manufacturing with EUVL at the 7nm logic node and the mid-10nm DRAM node. “EUV is the best platform for cost-effective density scaling and chip makers will make individual decisions based on their own processes to determine how to insert EUV, and node names will vary based on chipmakers unique conventions.”

Regarding extendibility of its EUVL platform, ASML is confident in its extendibility into the next decade. “The numerical aperture, currently 0.33, can be increased to above 0.5 with newly designed optics, which will improve the resolution from the current 13nm on the NXE:3400B to 8nm,” said Lercel (see Figure 2).

Figure 2

Source: ASML

“Such a high-NA system would provide the most cost-effective way for chipmakers to deal with the tighter tolerances at lower resolution and enable further device shrink.” He further noted that the company is in discussions with customers about the roadmap for high-NA systems and is targeting introduction between 2020 and 2023. “But exact timing is too early to tell and depends on customer demand.” (see Figure 3)

Figure 3

Source: ASML


Because lithography requirements are tightening to achieve optimum yield at smaller nodes, Lercel explained that the company’s holistic lithography approach integrates its lithography systems with metrology and computational lithography to provide a number of benefits, including controlling process-induced variations. “EUV will have the same level of control capabilities as DUV,” Lercel told SEMI.

Looking ahead, Lercel told SEMI that EUV will replace some of the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future. “Ultimately, DUV and EUV will be available in parallel for many years to come, and we remain committed to advancing both technologies to provide the mix that best meets customers’ performance and cost requirements.” To that end, the company says it will provide capabilities to match exposures done by both EUV and DUV to enable customers’ process flows in a mixed environment.

Points of contention

It would be unusual to have 100 percent agreement on just about any topic in the semiconductor industry, but EUVL readiness — or the potential for its future — for HVM has been particularly fraught with disparate view points for many years. Stephen Renwick, director of Imaging Physics at Nikon Research Corporation of America, told SEMI that EUVL insertion at the 7nm node is uncertain. “It still has inherent challenges in resist performance and the lack of a pellicle to protect its expensive masks,” said Renwick. He also pointed out that among the new challenges for EUVL is the suggestion that tool-specific optical proximity correction (OPC) will be required.

Renwick does allow that 193nm immersion multi-patterning lithography faces its own cost challenges, “but it is worth remembering that EUVL multi-patterning may be needed at the 7nm node and almost certainly at the 5nm node,” he said. “The need to keep costs low and reliability high will probably drive EUVL insertion to the later nodes.” Looking ahead to 5nm and below, Renwick told SEMI that the days of pattern shrinking being driven by lithography tools with other process partners only playing a supporting role are over. “Future-node patterning will require work in the optical printing and chemical processing realms, with new technologies like directed self-assembly (DSA). Making them a reality will require a concerted effort from multiple players.”

On a positive note, Renwick offers the reminder that the use of 193i or EUVL was never intended to be an either-or choice. “Reliance on only one technology is a bad solution,” said Renwick. “The future of lithography will require combinations of all our options. We happen to believe that 193i lithography will continue to be a centerpiece of those options.”

What about metrology at 7nm and 5nm?

Bryan Barnes, physicist at the National Institute of Standards and Technology (NIST) and project leader for the Optical Methods for 3D Nanostructure Metrology project, told SEMI that metrology applications at 7nm and 5nm will be more dependent upon an accurate understanding of the underlying physics of each individual metrology technique. “Often, combinations of multiple tools will be required to make critical measurements,” said Barnes. “The semiconductor industry is already facing challenges in process control where, for some features, no single methodology can provide adequate process control at high throughput.” NIST pioneered hybrid metrology techniques that have gained traction in the fab, noted Barnes. “These provide a statistical treatment for combining multiple metrology tools to achieve a single set of measurement values and uncertainties. I expect hybrid techniques to be an integral component of metrology moving forward.” 

Heading from 10nm down to 5nm, Barnes explained that the fundamental physics

of each metrology approach will play a larger role. As an example of this, a NIST project is addressing the accuracy of electromagnetic modeling for optical critical dimension metrology at the smaller dimensions. “My colleagues András Vladár and John Villarrubia are not only advancing experimental scanning electron microscopy, but also the modeling of the electron beam’s interactions with matter, yielding capabilities for the fitting of SEM images,” said Barnes.

With respect to metrology needed for multi-patterning at 7nm, NIST researchers Dan Sunday and Joe Kline recently published sub-nanometer resolved measurements of pitch walking in multi-patterned features using critical-dimension small-angle x-ray scattering (CD-SAXS). “That characterization was performed at a synchrotron, and there is great interest in developing more power light sources that would enable CD-SAXS measurements at the fab and potentially, in-line,” Barnes told SEMI.

Looking farther out to 5nm, Barnes noted that several methodologies will be required to realize accurate metrology. “Some of which may be in-line, while others will be off-line,” said Barnes. “Techniques that are inherently destructive will continue to augment not only dimensional metrology, but also the materials composition at the nanoscale.” To understand a device at 5nm, he believes that high-resolution techniques (e.g., atom probe tomography and scanning transmission electron microscopy), as well as lower resolution techniques (e.g., secondary ion measurement spectrometry) will be needed.

Some exciting challenges will have to be addressed, however, once the industry gets below 5nm. “Consider that a 1nm^3 volume of crystalline silicon has just 50 atoms,” said Barnes. The precise number of atoms across a 5nm-wide line depends upon the lattice orientation, but at these length scales, Barnes explained that dimensions can be expressed as few as ten atoms in width. “The process control needed for the line edge roughness control at 5nm becomes comparable to the silicon lattice constants.  Metrology must embrace measurements at near-atomic scales.”

Learn more about lithography programs and other sessions at SEMICON West 2017! Register now before price increase on May 12:


Global Update
May 9, 2017