Cost of Test: New Solutions and Strategies Revealed

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Cost of Test: New Solutions and Strategies Revealed

June 3, 2010 – Continued advances in semiconductor technology, coupled with the accelerated cost reduction demands of an increasingly consumer driven IC market have created the need for new and novel solutions and strategies for reducing the cost of test. Test suppliers and their customers can no longer depend on productivity and functional enhancements of traditional test solutions to achieve their cost reduction targets; they need revamped test paradigms and processes. Many of these new test paradigms will be explored at the industry’s major semiconductor test event, SEMICON West 2010.

Concurrent Test and Pushing the Limits of Parallelism

One of the challenges being explored will be the difficulties in implementing concurrent test and the physical limits of parallelism. Particularly in memory and logic, device-under-test (DUT) parallelism (that is, the number of DUTs tested in parallel at a test insertion), has been a primary method to reduce the cost of test in the context of device complexity, increased functionality, higher I/O and core speeds. And, as SOCs and SIPs become more integrated, with either multiple functions on a die or multiple die within a package, there is an opportunity to reduce test costs by testing multiple functions in DUTs simultaneously. This "Concurrent Test" capability can provide the same type of economic benefit as Multisite Testing (which can be done in conjunction with Concurrent Test). At the same time, there is a new challenge in that multiple test engineers can be working in parallel to develop tests for the different portions of the DUT. The challenges for implementing Concurrent Test include DFT capabilities, independent operation of various tester elements and the ability to manage complex test flows that are developed by multiple engineers – possibly working in different locations. Complicating the cost reduction objective is the concurrent need for reduced time to market, or TTM. At the SEMICON West 2010 Test session, Bruce Gravens of Teradyne will describe these challenges in more detail, illustrating the software and hardware elements in Automatic Test Equipment (ATE) to help facilitate this new type of testing.

Managing Interface Hardware and Socket Costs

The costs based on test and probe interface hardware and test sockets are becoming an increasing proportion of the overall test cost. There are a number of factors driving this, such as higher speed (Gb/s), more complex DUT I/O protocols, increased DUT parallelism, higher signal and power pin counts, and increased power delivery and signal channel fidelity requirements. One way to address these costs is through a new test concept called, “Test in Carrier,” or TIC. Bernhard Lorenz, the director of engineering at Multitest Electronic Systems GmbH, will describe a TIC solution that promises to reduce the cost of test while achieving the highest test parallelism with highest OEE at all temperatures and full package convertibility from large packages down to 1 mm x 1 mm wafer scale packages.

The TIC process enables test of singulated devices in very robust handling system offering a MUBA (Mean Unit Between Assist) in the range of 500,000, so operator assist interactions that can lead to human errors are minimized. The use of the carrier from Device Singulation, Burn In, AHC Test, and Marking to Final Packing in T&R additionally reduces operator interactions and enables full device traceability. To absolutely eliminate accidental mixing of devices, only automated machines can load and unload devices into and from the carrier, all carriers have machine-readable unique identification and the whole results of the process steps are mapped in a host.

Constant cost pressure requires new solutions for reduction of COT, for which the TIC approach offers very high test parallelism (up to 300x) and enables low investment per throughput. The robust handling of carriers instead of singulated devices enables one person to operate up to 20 test cells at high OEE. The standardized carrier minimizes the need of package-specific handler conversion, reducing non productive time and investment.

Accelerating Yield Ramps with On-Tester Scan Diagnosis

Test data usage for purposes beyond identifying whether a given die is good or defective has become essential for several reasons and drives a need for expanded, revamped, and better integrated test data systems and infrastructure. In addition, “adaptive test” methodologies that discriminately manage manufacturing process variations while simultaneously eliminating redundancies to new levels are increasing in importance as a source for cost reduction. The need for better integrated usage of test data for fab process yield learning, and feedback within a more distributed manufacturing test are all becoming essential applications in advanced IC test areas.

As part of this field of rich, adaptive data sets that can reduce defects and improve yield, Colin Ritchie from Verigy will discuss how fast and reliable scan chain diagnosis on production ATE quickly identifies yield-limiting issues on advanced nanometer devices. Complementing the results from optical inspection, other process control tools, and actual device failure analysis, the on-tester scan chain analysis adds ‘electrical inspection’ to the fab metrology tool box. These new tools help map electrical failures to elusive physical defects, which can be difficult to localize with traditional methods. Results are available directly from the production test so the time to defect root cause diagnosis can be significantly shortened – accelerating the device ramp-up and reducing time-to-yield.

Be sure to mark your calendar for these test events at SEMICON West 2010:

Test Challenges
Tuesday, July 13, 10:30am–12:20pm
TechSITE North, North Hall

Test Solutions
Wednesday, July 14, 10:30am–12:30pm
TechSITE North, North Hall

IEEE ATEVision 2020 Workshop
Thursday, July 15, 9:00am–5:00pm
San Francisco Marriott Marquis