Bonded Wafers for Three-Dimensional Integration

By Rich Allen, North America 3DS-IC Technical Committee Chapter Co-Chair

Three-dimensional (3D) integration is a key enabling technology for compact, high-performance, and/or low-power electronics. This technology enables the fabrication of circuits with functions that commonly cannot be fabricated on a single substrate in a smaller 3D footprint, a key consideration in portable and wearable devices, or can enable higher density of transistors in a 3D footprint, a key consideration in high-performance computing. 3D stacking, in turn, is enabled by wafer bonding, whereby two or more wafers are bonded into a single “device”, which can then be inserted into a system.

Two SEMI Standards Committees, 3D-Stacked Integrated Circuits and MEMS, are actively developing standards for the Bonded Wafer community. Standards related to wafer bonding generally fall into one of the following four areas:

  1. Starting materials with properties required for bonding applications. An example of this is SEMI 3D2, Specification for Glass Carrier Wafers for 3DS-IC Applications. The core of 3D2 is a table showing the parameters that must be considered when specifying glass wafers for use in a temporary bonding process.
  2. Intermediate materials. This includes processed wafers ready to be inserted into a wafer bonding process as well asbonded wafer stacks awaiting additional processes, including bonding to additional wafers.
  3. Processes common to all wafer bonding applications. This includes alignment between multiple wafers and/or chips and shipping of thinned wafers
  4. Metrology for characterizing bonded wafers. An example is a set of three documents focused on bond void metrology: One is published standard, SEMI 3D13, Guide for Measuring Voids in Bonded Wafer Stacks; this document provides a snapshot of the capabilities of the various tools available for identifying and characterizing voids.  The second, SEMI AUX-032, Round Robin Study of Method for Measurement of Voids in Bonded Pairs of Silicon Wafers; this companion document to 3D13 describes detailed results from an interlaboratory experiment to characterize voids on a common test structure. The final document, currently being balloted, SEMI 5822, New Standard: Specification for Reference Material for Bonded Wafer Stack Void Metrology, standardizes the test structure used is the Round Robin experiment, with the goal of facilitating adoption of wafer bonding through the semiconductor industry.

While wafer bonding is a promising topic, both committees continue to develop standards related to wafer bonding, with the following documents under development:

  1. SEMI Draft Document 5173, New Standard: Guide for Describing Silicon Wafers for Use in a 300 mm 3DS-IC Wafer Stack.  This document is being developed to complement other SEMI standards for silicon starting material, recognizing that the existing specifications do not meet the needs for 3D stacking.
  2. SEMI Draft Document 5800, New Standard: Guide for Wafer Edge Trimming for 3DS-IC Process
  3. SEMI Draft Document 6075, New Standard: Guide for Describing Glass-Based Material for Use in 3DS-IC Process
  4. SEMI Draft Document 6076, New Standard: Specification for Identification and Marking on Wafers and Wafer Stacks for 3DS-IC Applications.  Each wafer is commonly marked by the manufacturer with a unique identifier, which is used at various stages during processing. However, after bonding, multiple markings may be present or the markings may be hidden by the bond or removed during thinning.  This document will provide standard procedure for associating a specific wafer with its process history.
  5. SEMI Draft Document 6018, New Standard: Specification for Silicon Substrates used in fabrication of MEMS Devices


Get Involved

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If you have any questions regarding SEMI 3DS-IC Standards activities, please contact your local SEMI Standards staff.


Standards Watch
March 2, 2017