Standards Update on 3D ICs and TSVs
Standards Update on 3D ICs and TSVs
By James Amano, Director, SEMI International Standards
Update: Presentations from the 3D IC Technology Forum recently held at SEMICON Taiwan are now available online – click here.
Three-dimensional integrated circuits (3D ICs) – composed of a stack of two-dimensional die – are increasingly cited as being part of the solution to the semiconductor industry keeping pace with Moore’s Law. While current integration schemes such as wire bond and flip chip have been in production for some time, the next generation of 3D integration incorporates through-silicon via (TSV) technology as the primary method of interconnect between the die. TSVs are one of the most rapidly developing technologies in the semiconductor industry and promise a fundamental shift for current multi-chip integration and packaging approaches. Without manufacturing standards, however, cost-effective, high-volume manufacturing will be difficult to achieve. As Ms. Urmi Ray of Qualcomm’s Advanced Technology & Integration Group states, “A key to the success, cost-effectiveness and early adoption of 3D TSV technology is development of technical standards.”
3D ICs have the potential for increased performance, smaller footprints, and reduced cost and power consumption. However, multiple manufacturing challenges must first be solved, as 3D ICs’ increased design and mechanical complexity can lead to signal interference, increased manufacturing defects, and thermal management issues. In order to gather industry input and identify potential standardization topics, SEMI and SEMATECH hosted a 3D Interconnect Challenges and Need for Standards Workshop during SEMICON West. This workshop identified areas of concern for 3D TSV integration and the gaps between existing technologies and future solutions. Speakers also shared their experiences dealing with TSV-connected die and wafers as well as thin wafer handling and shipping.
The workshop aimed for a better understanding of how new and existing wafer metrology technologies can be utilized, modified or enhanced to measure and improve 3D interconnect processes. Participants came from all industry segments: foundries, OSATs, IDMs, Fabless, research institutions and equipment and material vendors such as TSMC, UMC, Amkor, ASE, Samsung, Qualcomm, ITRI, IMEC, Applied Materials, Novellus, KLA-Tencor, Brewer Science, and 3M.
Applicability of current standards was also discussed, as several SEMI Standards were referenced and could easily be adapted or modified for use with bonded wafers. One of the speakers, Andy Rudack of SEMATECH said “I am now violating SEMI Standards about 25 times a day” in his attempt to use current single wafer standards while processing multiple bonded wafers. For example, bonded wafer pairs used for 3D interconnect and TSVs often violate the parameters specified in SEMI M1.15 and in the multiple SEMI Standards that reference SEMI M1 as an applicable Standard, for topics such as edge trim, thickness, and identification marking. Thinned wafer handling also has multiple challenges to overcome, such as factory-to-factory transport, handling during debonding, handling at the die singulation stage, and die pick/place during flip chip construction.
This workshop was the first step towards putting together a SEMI Standards Working Group to focus on well-timed standardization of processes, equipment, and materials. Successful development of needed Standards will require collaboration and participation across the supply chain, particularly more communication and information sharing between the design, test, and manufacturing communities, to accelerate market adoption. In addition, communication between SEMI and other SDOs will be vital in harnessing expert resources.
The outcome of this workshop was the identification of three target areas to focus standardization efforts within SEMI: Bonded Wafer Pair, to be led by Andy Rudack, SEMATECH; Inspection/Metrology, to be led by Chris Moore, Semilab; and Thin wafer handling/shipping to be led by Urmi Ray, Qualcomm. Topics to be addressed within each area are:
- Wafer weight/robotic end effectors
- Cross slot/double slotted wafer alarms
- Damage in wafer carriers –FOUPs/FOSBs
- Wafer handling errors/damage/breakage
- Via depth control
- Ability to measure depth accurately and consistently
Wafer bumping induced failures (Foundry, IDM, OSAT)
- Wafer thinning: via reveal and wafer stress failures
- Thinned wafer handling: sputter, WSS
Assembly induced failures (Foundry, IDM, OSAT)
- Die joining: chip-chip, chip-wafer, chip-substrate
- Module joining: die to wafer, die to die, die stack to substrate
Test induced failures (Foundry, IDM, OSAT)
- Pressure, contact damage, etc
Current plans are to continue dialogue among the stakeholders during SEMICON Taiwan. For further information, please contact me at firstname.lastname@example.org.
August 3, 2010
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