3D ICs and TSVs
3D ICs and TSVs
By James Amano, SEMI
Three-dimensional integrated circuits (3D ICs) – composed of a stack of two-dimensional die – are increasingly cited as being part of the solution to the semiconductor industry keeping pace with Moore’s Law. While current integration schemes such as wire bond and flip chip have been in production for some time, the next generation of 3D integration incorporates through-silicon via (TSV) technology as the primary method of interconnect between the die. TSVs have been one of the most rapidly developing technologies in the semiconductor industry and promise a fundamental shift for current multi-chip integration and packaging approaches. Without manufacturing standards, however, cost-effective, high-volume manufacturing will be difficult to achieve. As Ms. Urmi Ray of Qualcomm’s Advanced Technology & Integration Group states, “A key to the success, cost-effectiveness and early adoption of 3D TSV technology is development of technical standards.”
3D ICs have the potential for increased performance, smaller footprints, and reduced cost and power consumption. However, multiple manufacturing challenges must first be solved, as 3D ICs’ increased design and mechanical complexity can lead to signal interference, increased manufacturing defects, and thermal management issues. In order to gather industry input and identify potential standardization topics, SEMI and SEMATECH will be hosting a 3D Interconnect Challenges and Need for Standards Workshop during SEMICON West. This workshop will report recent progress, identify areas of concern for 3D TSV integration, and identify the gaps between existing technologies and future solutions. Participants will also share their experiences dealing with TSV-connected die and wafers.
The workshop aims for a better understanding of how new and existing wafer metrology technologies can be utilized, modified or enhanced to measure and improve 3D interconnect processes. Practical experience with wafer bonding, thin wafer handling, and metrology results for actual 3D interconnect processing will be shared. Applicability of current standards will also be discussed, as several SEMI Standards may be easily adapted or modified for use with bonded wafers. For example, bonded wafer pairs used for 3D interconnect and TSVs often violate the parameters specified in SEMI M1.15 and in the multiple SEMI Standards that reference SEMI M1 as an applicable Standard, for topics such as edge trim, thickness, and identification marking. Thinned wafer handling also has multiple challenges to overcome, such as factory-to-factory transport, handling during debonding, handling at the die singulation stage, and die pick/place during flip chip construction.
As with all Standards work, timing is critical. Premature standards, when the technology is still changing rapidly, are constraining and stifle innovation, and when standards are too late, similar but competing technologies and products can cause confusion. However, well-timed standardization of processes, equipment, and materials leads to increased efficiency and reduced cost, making the entire solution more viable commercially.
This workshop is the first step towards putting together a Standards Working Group. Successful development of needed Standards will require collaboration and participation across the supply chain, particularly more communication and information sharing between the design, test, and manufacturing communities, to accelerate market adoption. In addition, communication between SEMI and other SDOs will be vital in harnessing expert resources. I encourage all members of the industry involved in front-end wafer processing as well as the packaging community to get involved in this vital activity.
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