An Update on 450mm Activities in SEMI Standards
An Update on 450mm Activities in SEMI Standards
By Ian McLeod, SEMI North America
2010 is a significant year in 450mm wafer standards document development. The SEMI Standards program is overseeing increasing document development activities related to 450mm-related standards reflecting the increased attention and interest being given by the SEMI Standards volunteers.
“Industry volunteers establishing standards on wafer specifications brings us back to the roots of the original SEMI Standards program. With mechanical handling wafer, carrier, and loadport specifications in place, the industry can cost-effectively continue the initial research and development of interfaces, processes, materials, and equipment which would eventually be required for semiconductor manufacturing on 450mm wafers.” – John Ellis, Vice President, SEMI, Global Standards and Technology
Specifications for 450mm front-opening unified pods (FOUPs) (SEMI E158-0710) and loadports (SEMI E154-0310) have been developed to be used together, and are already available. Also, a specification for the interface between stockers and transport components has just been published as SEMI E156-0710.
While specifications for circuit-quality 450mm wafers are not yet in development, specifications have been published for both mechanical handling wafers (SEMI M74-1108), which are used for R&D and semiconductor equipment (e.g., wafer carriers, loadports, AMHS) design investigation, and single crystal wafers (SEMI M76-0710), which are used for process and metrology equipment R&D.
The single crystal wafers specified in SEMI M76 can also be used to establish the techniques and metrology necessary to support a dimension specification for circuit-quality 450mm wafers. For the 450mm wafer size, edge profile and flatness need to be refined further than what has been used for smaller wafer sizes, and specifications for each of these are in development as Draft Documents 4588 and 4812, respectively.
A specification for a front-opening shipping box (FOSB) is under development (Draft Document 4760), along with a specification for a new carrier for 450mm wafers, the Multi-Application Carrier (MAC) (Draft Document 4770). The MAC is focused on silicon manufacturing and processed wafer shipping and is designed to be compatible with both loadports and especially FOUPs, using the same envelope, factory integration, and interoperability interfaces. Draft Documents 4980 and 4981 modify SEMI E154 and SEMI E158 respectively to provide strong integration between FOUPs, carriers, MACs, and FOSBs.
On the assembly and packaging side, document development is in progress for specifications for tape frames (Draft Document 4815), frame cassettes (Draft Document 4814), and load ports for frame carriers (Draft Document 4965).
The expertise required for these documents is diverse, but in order for these documents to be usable together, there has to be cooperation across the technical committees sponsoring their development. The image below shows where development is taking place.
For more information
Naturally, SEMIViews customers already have access to all of the published standards in this article. Anyone interested in purchasing the individual standards can use the links below to find each standard in our store:
SEMI E154-0310, Mechanical Interface Specification for 450 mm Load Port
SEMI E158-0710, Mechanical Specification for Fab Wafer Carrier Used to Transport and Store 450 mm Wafers
(450 FOUP) and Kinematic Coupling
SEMI E156-0710, Mechanical Specification for 450 mm AMHS Stocker to Transport Interface
SEMI M74-1108, Specification for 450 mm Diameter Mechanical Handling Polished Wafers
SEMI M76-0710, Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers
To participate in development of the draft documents mentioned here, please contact your local SEMI Standards staff. For additional information on these activities, see the Standards New Activity Report Forms (SNARFs) linked below.
4588, New Standard: Guide for Specifying Edge Profile of 450 mm Silicon Wafers
4812, New Standard: Guide for Flatness Measurement on 450 mm Wafers
4760, New Standard: Mechanical Specification for 450 mm Shipping Box Used to Transport and Ship 450 mm Wafers
4770, New Standard: 450 mm Horizontal Multi-Application Carrier
4980, Revision to SEMI E154, Mechanical Interface Specification for 450 mm Load Port
4981, Revision to SEMI E158, Mechanical Specification for Fab Wafer Carrier Used to Transport and Store 450 mm Wafers (450 FOUP) and Kinematic Coupling
4814, Specification for Frame Cassette for 450 mm Wafer
4815, Specification for Tape Frame for 450 mm Wafer
4965, Specifications for Load Port for 450mm Frame Carrier
About the Silicon Wafer, Physical Interfaces & Carriers, and Assembly & Packaging Committees
Physical Interfaces & Carriers Committee
This committee develops specifications to enhance the manufacturing capability of the semiconductor industry, specifically addressing mechanical, electrical, and special equipment specifications; and material movement integration, including substrate support and containment structures. For more information on committee activities, please contact Ian McLeod at firstname.lastname@example.org or Hiro'fumi Kanno at email@example.com.
Silicon Wafer Committee
This committee develops international standards fulfilling the requirements for commercial silicon wafers. Silicon Wafer Committee standardization includes specifications and guides for silicon wafers, test methods for silicon wafer quality and geometry, shipping box related topics, wafer ID related topics, and business related topics to support smooth communication between silicon suppliers and customers. For more information on committee activities, please contact Kevin Nguyen at firstname.lastname@example.org or Akiko Yamamoto at email@example.com.
Assembly & Packaging Committee
This committee develops specifications to enhance the manufacturing capability of the semiconductor industry as it relates to the packaging and assembly of the semiconductor chip, including the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration. This committee also discusses total infrastructure for Chip to Final Set system and processes such as Testing and Design Software, Transportation Tools, Reliability and Traceability issues, EHS issues, Inspection methods, etc. For more information on committee activities, please contact Paul Trio at firstname.lastname@example.org or Hiro'fumi Kanno at email@example.com.
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