Standards Related Programs in Conjunction with SEMICON Japan 2009


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Standards Related Programs in conjunction with SEMICON Japan 2009

Tuesday, December 1, 2009 9:00-12:00
International Conference Room, International Conference Hall, Makuhari Messe
Sponsored by International SEMATECH Manufacturing Initiative (ISMI)
Supported by SEMI
Free of charge. *Pre-registration required.
Program Chair: Harvey Wohlwend, ISMI

Program Overview
This workshop will provide the vision, progress, and roadmap for next generation factories as well as reports on enabling implementations and deployment experiences. The latest Interface A, data quality/time synch, predictive maintenance, and EEQA requirements and experiences will be shared. This workshop provides an opportunity to further align IC manufacturers and suppliers in their Next Generation Factory and e-Manufacturing implementation strategies as the semiconductor industry strives to continuously improve factory productivity.

Tuesday, December 1, 2009 10:00-17:30
Conference Room, Oshima Building 5F, SEMI Japan
Fee (tax included):
Until Fri. Nov. 20: JPY 21,000 / After Fri. Nov. 20: JPY 25,000
Includes 5% tax, lunch and proceedings (available both in Japanese and English). Conducted in Japanese only. No interpretation provided.

Program Chair: Kenji Sugihara, Panasonic Factory Solutions

Program Overview
This seminar is a two-part introduction to SEMI S2, a safety guideline for semiconductor manufacturing equipment, which has been widely adopted around the globe and was revised in July of this year. The first part introduces the fundamental criteria of SEMI S2 and its philosophy. Part two provides detailed explanation on a specific area (choose one to attend from electrical/ chemical/ mechanical area) using concrete examples. There will also be ample opportunity for discussion with the presenters.

Wednesday, December 2, 2009 10:30-15:00
SEMI Feature Zone Presentation Stage, Makuhari Messe
Supported by Strategic Standard WG, Semiconductor Technology Committee, Japan Electronics and Information Technology Industries Association (JEITA)
Free of charge. *Pre-registration required.
Conducted in Japanese and partly in English. No interpretation provided.

Program Chairs
Youichi Iga, NEC Electronics Corporation
Kiyokazu Iida, Fujitsu Micronics Limited

Program Overview
SEMI, SIA and JEITA have been working to standardize technology employing unique identifiers to enhance traceability in order to prevent counterfeiting of semiconductors. Currently, efforts are underway to establish an ISO standard to make these technologies available to all industries. This workshop will review recent developments involving organizations in the U.S. and Japan, and explore their potential business impacts.

Wednesday, December 2, 2009 13:00-17:00
International Conference Room, International Conference Hall, Makuhari Messe
Fee (tax included):
Until Fri. Nov. 21: JPY 16,000 / After Fri. Nov. 21: JPY 19,000
Includes 5% tax, proceedings (available both in Japanese and English). Conducted in Japanese only. No interpretation provided.
Program Chairs
Supika Mashiro, Canon Anelva Corporation
Hidetoshi Sakura, Intel Corporation

Program Overview

SEMI S22 details electrical safety criteria of semiconductor manufacturing equipment safety design in conformance to SEMI S2. SEMI S26 also refers S22 for electrical safety design criteria for FPD manufacturing system. This program will illustrate points for S22 implementation for electrical safety design that satisfies S2/S26 and conforms to other major international electrical safety requirements applicable to the industry.

Wednesday, December 2, 2009 13:30-17:00
International Conference Room, International Conference Hall, Makuhari Messe
Supported by: NPO Japan ESD Association
Fee (tax included):
Until Fri. Nov. 20: JPY 16,000/ After Fri. Nov. 20: JPY 19,000
Includes 5% tax and proceedings. Conducted in Japanese only. No interpretation provided.
Program Chair
Toshiro Murakami, Murakami Corporation

Program Overview
The damages caused by electrostatic discharge(ESD)and electrostatic attraction (ESA) caused by electrostatic phenomena are existing as critical issue and it is requested to take more comprehensive countermeasures to reduce these problems in Semiconductor Manufacturing processes. This program will introduce SEMI E78 standards and the measuring methods as countermeasures of ESD by a demonstration.

Thursday, December 3, 2009 13:00-16:00
International Conference Room, International Conference Hall, Makuhari Messe
Supported by Fraunhofer IIS-b
Fee (tax included): JPY 5,000
Includes 5% tax. Conducted in English and partly in Japanese. No interpretation provided.
Program Chairs
Lothar Pfitzner, Fraunhofer IIS-b
Richard Oechsner, Fraunhofer IIS-b
Mikio Furukawa Shin-Etsu Polymer

Program Overview
This workshop focuses on improvements to yield models, yield learning, contamination control, equipment efficiency, equipment assessment and cost of ownership as they relate to the field of metrics, with a view toward their standardization for next-generation fab (e.g., 450mm). There will be reports from Japan and Europe, and opportunity for discussion on a global level.

Thursday, December 3, 2009 13:00-17:00
International Conference Room, International Conference Hall, Makuhari Messe
Fee (tax included):
Until Fri. Nov. 21: JPY 16,000 / After Fri. Nov. 21: JPY 19,000
Includes 5% tax, and proceedings (available in English). Conducted in Japanese and partly in English. No interpretation provided.
Program Chairs

Naoyuki J Kawai, Senior Engineer, Process & Device Analysis Engineering Development Dept. Process Technology Development Div. Production and Technology Unit., Renesas Technology Corporation
Michio Tajima, Director, Department of Spacecraft Engineering Institute of Space and Astronautical Science, Japan Aerospace Exploration Science (JAXA)

Program Overview

  • Introduction of SEMI Standards and year-end forecasts and updates on semiconductor, semiconductor capital equipment and materials markets
  • Edge and Near-Edge Geometry Specification in SEMI Standard
  • Characterization of Wafer Bevel Film Cut Position for Effective Immersion Lithography
  • Bulk Edge Profile Impact on SOI Characteristics