Paolo Gargini Keynote to Address the “Era of Equivalent Scaling” at STS 2007


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Paolo Gargini Keynote to Address the “Era of Equivalent Scaling” at SEMI Technology Symposium 2007

Symposium to be held December 5-7, 2007 at the Makuhari Messe in Chiba, Japan; Registration now Open

TOKYO, Japan-October 1, 2007 - SEMI will hold the annual SEMI Technology Symposium (STS) 2007, December 5-7, 2007 at the International Conference Hall, Makuhari Messe, in Chiba. The STS keynote speech entitled "Welcome to the Era of Equivalent Scaling" will be made by Paolo A. Gargini of Intel, at the Convention Hall on the International Conference Hall 2 in Makuhari Messe, on December 5, 13:15-13:55. Attendance is free of charge, and advance registration is not necessary. Visitors may enter the hall without paying admission on the day.

During this year’s STS, a special session of the ITRS will be held as a joint program between STS and ITRS (International Technology Roadmap for Semiconductors) on the first day of the show. The ITRS has been developed by the Big Five (Europe ESIA, Japan JEITA, Korea KSIA, U.S. SIA Taiwan TSIA), and provides a detailed analysis of future semiconductor technologies proposed in the next fifteen years. In this session, topics include front loading of High-k gate films, and More than Moore as a direction of diversification.

"Memory" and "Microsystem/MEMS" will also be added to the STS. See below for more information on the program contents of STS.

"STS is a well known event for its unique nature, with both the loftiness of the academic environment and casual atmosphere of a symposium. Last year, it celebrated its 25th anniversary, and this year, it will open a new page toward its next 25th anniversary,” said Manabu Tsujimura, STS 2007 program chairman, and senior executive officer, division executive, Semiconductor Equipment Division, Ebara Corp. “This year's STS will begin with looking down upon the future of the semiconductor in collaboration with ITRS.”

“Against the future prospects shown here, well-known engineers and scientists in each field will offer their promising solutions. Let's think of the future of the semiconductor together through this year's STS," said Tsujimura.

STS is the biggest SEMI technical symposium, and is held in conjunction with SEMICON Japan every December, providing a forum for both the device manufacturers and equipment and materials suppliers from around the world to exchange their views of technology trends. The symposium was launched in 1982, and this year marks its 26th anniversary. At the STS, current technical trends, technical issues, and practical technologies focused on the semiconductor process and devices, will be presented by first-line engineers. Last year, STS was comprised of nine technical sessions with 88 seminars, besides a keynote speech, and it had 1,024 people in the gross audience.

Registration for STS 2007 is currently available at our Web site at www.semiconjapan.org. Inquiries regarding STS 2007 will be answered at SEMI Japan Events Registration (Tel: 81-3-3222-5993, or Email: jeventinfo@semi.org).

SEMI is a global industry association serving companies that provide equipment, materials and services used to manufacture semiconductors, displays, nano-scaled structures, micro-electromechanical systems (MEMS) and related technologies. SEMI maintains offices in Austin, Beijing, Brussels, Hsinchu, Moscow, San Jose (Calif.), Seoul, Shanghai, Singapore, Tokyo and Washington, D.C. For more information, visit www.semi.org.

References

SEMI Technology Symposium (STS) 2007 at a glance

    Session: December 5-7, 2007

    Venue: The International Conference Hall in Makuhari Messe (Chiba City)

    Sponsor: SEMI

    Program Chairman: Manabu Tsujimura, the STS 2007 program chairman and senior executive officer, division executive, Semiconductor Equipment Division, Ebara Corp.

    Registration: Available from October 1, at the SEMICON Japan 2007 Web site:http://www.semiconjapan.org

Programs:

Keynote Speech by Paolo A. Gargini of Intel

"Welcome to the Era of Equivalent Scaling"

Moore’s law has been the most powerful guiding principle in the semiconductor industry for more than 40 years. Scaling down the device geometry has been the enabler of low-cost, high-performance, and low-power integrated circuits. Recently, however, straightforward geometrical scaling does not lead to higher performance and less power at the same time; together with geometrical scaling, we need equivalent scaling. The definition of equivalent scaling is to enable better scaled integrated circuits by using new materials, new process technologies, new device structures, and novel 3-dimensional memory cell structures which realize smaller cell area, etc. We will present the types of new technologies required in the era of equivalent scaling.

STS Special Session: ITRS Public Conference

The International Technology Roadmap for Semiconductors, known as the “ITRS,” is the fifteen year assessment of the semiconductor industry’s future technology requirements and potential solutions. In 2007, the ITRS celebrates its tenth year. This STS special session ”ITRS Public Conference” explains the newly released version of ITRS 2007, starting with Overall Roadmap Technology Characteristics and followed by working group presentations: Process Integration, Devices, and Structures; RF and Analog/Mixed-signal Technologies for Wireless; Emerging Research Devices (ERD); Emerging Research Materials (ERM); Metrology, System Drivers and Design; Environment, Safety, and Health; Front End Processes; Test and Test Equipment; Interconnect; Factory Integration; Yield Enhancement; Lithography; Modeling and Simulation and Assembly and Packaging.

Session 1 – Memory New Period of Memory Device Competition! – Who will Win the Game? –--

Memory market encompassing DRAM and NAND Flash is expanding steadily, triggered by emerging new applications and growing consumption in Emerging Countries. Amid such circumstances, the industry is locked in fierce development competition to pursue higher device integration through further miniaturization while cost-per-bit is hovering at a high level. Meanwhile development of new memory technologies is making good progress. PRAM, for example, is currently at the stage of final preparation for volume-production ramp-up. When becoming fully production-worthy, PRAM may compete against the existing memory devices in the market.

Taking such current status into account, this session will present future memory business trend, memory device manufacturers’ strategies and updates on development of various new memory technologies.

Session 2 – Microsystem / MEMS - Topics, Materials and Equipments for MEMS -

Small-sized and high-performance devices termed Microsystems or MEMS fabricated through a combination of silicon micromachining and various other technologies are used as key components such as sensors in a broad range of application fields. Following the previous ten “Microsystem / MEMS Seminars,” this session is renamed as “the 11th Microsystem / MEMS Session” and will be held as a part of the SEMI Technology Symposium (STS). The session will present the latest information on emerging topics, materials and equipment for MEMS.

Session 3 – Multi-Level Interconnection & Etching – A Breakthrough Technology to Achieve the High Performance Interconnect Process and Highly Variability-controlled Etching Process.

This year’s Multi-Level Interconnection & Etching Session will first provide a high-level ITRS overview of technology trend beyond the 45 nm node, and then present specific enabling technologies such as Cu/low-k technology and CMP technology as well as air-gap technology whose potential in volume-production line has been actively studied in recent years. As next-generation interconnection technologies, this session will pick up optical transmission technology and TSV (through-silicon via) technology. In the etching process, process variation control including LER/LWR reduction will become increasingly important. In addition to etching technologies relating to multi-level interconnection, like in the last year’s session, this session will highlight critical layer etching such as gate fabrication which becomes more and more demanding along with miniaturization of IC devices.

Session 4 – Lithography & Mask – Has Immersion Lithography Taken Off Yet –

Immersion lithography system with NA of higher than 1, the leading-edge lithography system, has been installed in volume-production line and is now in operation. It is said that a number of problems specific to immersion lithography have been solved in a short period of time. Have all of the problems been really cleared? This session will reveal a real capability of immersion lithography. We will present current circumstances of immersion lithography and on-going innovation of advanced masks whose price is soaring.

Session 5 – Manufacturing Science – 300mm Prime & 450mm for Next-Generation Factory – What is Next-Generation Factory –

Our industry has started addressing 300mm prime Factory and 450mm wafer Factory. This session will discuss “What is Next-generation factory?,” “What will IC maker, tool, AMHS and software vendors be expected to do?” and “What are required to respond to changes in the environment to surround the semiconductor industry, ongoing device scaling trend and introduction of high-mix small-lot production system?”

This session will identify requirements for next generation factory of different people with different roles in manufacturing process. We will discuss “What kind of Next-generation factory do the ISMI and JEITA guidelines look for?,” “What advantages will such Next-generation factory bring to IC maker, tool, AMHS and software vendors?” and “How will different companies realize alliance across the boundaries?”

Session 6: Testing - Developing Technology and Methodology - Challenge to the best Quality –

Ushering in the DSM (deep submicron) era, along with accelerated IC device evolution to higher performance, functionality and precision, we are making continuous efforts toward a challenge to develop more advanced testing technology to ensure high reliability of IC devices. In order to successfully overcome this challenge, it is essential to build and maintain collaboration among diversified technology areas including DFT (design for testing) and metrology both of which drive cost reduction, ultra-high-speed signal testing technology, peripheral technologies of metrology which are the keys to enhance measurement reliability, and defect analysis technology. This session will invite those who are active in the front lines and ask them to present the latest research achievements and technology trends.

Session 7: Lithography and Mask – 32nm: Does Double Patterning Have the Early Lead? –

Nothing is clear yet about lithography technology beyond the next generation. In addition to those technologies which sound familiar, such as EUVL, high-index immersion lithography, ML2 (mask-less lithography) and imprint lithography, novel concepts including self-assembly method are proposed as well. At present, extension of ArF lithography (through combination of immersion lithography and double exposure / double patterning) seems to have a lead over the other technologies. Looking from a different viewpoint, however, double exposure / double patterning poses a new challenge to mask technology. In particular, it becomes necessary to address overlay accuracy and CD control requirements and take note of DFM (design for manufacturing) required for mask data processing. This session will look toward the future of lithography technology including mask technology.

Session 8: Advanced Device – 45nm/32nm node device and process technology –

In advanced devices, including 45nm node for mass production and 32nm node under research and development, with scaling, it is difficult to satisfy simultaneously needs for performance, power dissipation, variation, and cost.

To solve these problems, advanced device and process technology, such as high-k gate dielectrics and metal gate material, has been developed aggressively.

On the other hand, semiconductor devices are used in the wide application, such as high voltage device for automobile.

In this session, engineers in the forefront will talk about above-mentioned device and process technology.

Session 9: Packaging – Progressing 3D Jisso Technology / LSI Embedded vs. CoC vs. TSV –

Diversification of electronic device applications and integration of required functions / technologies are heading for an arena which an advanced SOC will be hardly able to realize on its own. As a result, SiP innovation is shifting to increasingly advanced 3D packaging technology.

This year’s Packaging Session will focus on 3D-SiP which adopts TSV (through-silicon-via) technology, CoC (chip-on-chip) which is a non-TSV stacking technology, and LSI embedded substrate. We will discuss advantages and future potentials of these technologies which have just started to be mobilized in volume-production lines one after another. As happened in the past, an expert with a great knowledge of the IC packaging technology will serve as a session chair and provide a comprehensive explanation of these technologies. We will invite speakers from European institutions such as IZM and IMEC. This session will allocate sufficient time for panel discussion. Please join us in Package Session and actively take part in the discussion.

Association Contacts:

Programs Division, SEMI Japan
Tel: 81.3.3222.5993
E-Mail: jeventinfo@semi.org

Scott Smith, SEMI US
Tel: 1.408.943.7957
E-mail: ssmith@semi.org



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