SMC 2006 Day Two Report
Japanese Consortium Helps Cut Costs for Materials Suppliers
Flip Chip Blurs the Borders between Fab and IC Packaging
Half Moon Bay, California, January 13, 2006 -- Attendees on the second day of the SEMI Strategic Materials Conference (SMC) 2006 learned how Japanese materials suppliers joined together to cut costs, and were given an optimistic outlook on the convergence of front-end and back-end processes in chip making.
Yoshifumi Kawamoto, director general manager, R&D department, CASMAT, outlined the formation of CASMAT, an R&D consortium established in 2003 by Japanese materials suppliers. Member companies include JSR, Sumitomo Chemical, Sekisui Chemical, Tokyo Ohka Kogyo, Nitto Denko, Hitachi Chemical, Toray Industries and others.
The consortium operates a 1,300 square meter clean room equipped with 300mm wafer technology for 65-nanometer back-end of line (BOEL) processing.
The motivation for forming CASMAT was to give materials suppliers access to the expensive equipment necessary to develop integrated solutions, according to Kawamoto. “Materials suppliers need equipment to develop integrated solutions but the cost of the equipment is too high,” he said.
Under the consortium model, member companies develop new materials and CASMAT undertakes the evaluation of the materials. This accelerates development time and allows device makers to get their products into production earlier.
CASMAT is focused on four key areas: low-k materials, CMP slurries and pads for copper/low k interconnects, buffer coat organic material, and back grind tape and dicing tape for the assembly process.
Kawamoto noted that to continue its success CASMAT needs to undertake further collaborations with other consortia, device makers and equipment suppliers.
Arthur Zafiropoulo, chairman and CEO of Ultratech, told SMC 2006 that the border between wafer fabrication and device packaging was getting blurred because leading edge flip chip, wafer level package and post passivation technologies increasingly use front-end fab processes.
Advanced packaging will grow at 20 percent CAGR from 2005 to 2008 and flip chip technology will enable next generation portable and high performance electronic products, according to Zafiropoulo.
Currently 10 percent of all wafers are bumped, growing to an estimated 35 percent by 2010. The cost of bumping dropped below the cost of wire bonding in 2003, but wire bonding will never go away completely, said the Ultratech CEO.
A typical 300mm bump line producing 10K wafers per month would cost around $30 million, and uses many of the same processes found in the front-end, including lithography, sputtering, strip and etch. “Now the back-end in flip chip seems just like the front-end, but it’s a lot cheaper,” said Zafiropoulo. Further, he believes these lower cost bumping fabs will begin to sprout up in China, outpacing local investments in wafer fabs which can cost up to $3 billion.
SEMI is a global industry association serving companies that provide equipment, materials and services used to manufacture semiconductors, displays, nano-scaled structures, micro-electromechanical systems (MEMS) and related technologies. SEMI maintains offices in Austin, Beijing, Brussels, Hsinchu, Moscow, San Jose (Calif.), Seoul, Shanghai, Singapore, Tokyo and Washington, D.C. For more information, visit www.semi.org.
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