With the Uncertainty of Moore’s Law, Industry Expands 3D IC Development
Moore’s Law may not be dead, but it is terminal, according to Gordon Moore
June 3, 2010 – “It can't continue forever,” said Moore himself. “The nature of exponentials is that you push them out and eventually disaster happens. In terms of size [of the transistor], you can see that we’re approaching the size of atoms, which is a fundamental barrier, but it’ll be two or three generations before we get that far– but that's as far out as we’ve ever been able to see.”
Today, 3D packaging with TSV interconnects offers a scaling pathway around Moore’s Law, and the industry is fast developing the tools, processes and technologies necessary to implement 3D in both stacked memories and heterogeneous packages. According to Yole Développement, there are currently 15 different 300 mm 3D IC pilot lines currently running or being installed, spanning R&D centers, packaging houses, CMOS foundries, and inside IDM fabs. Initiatives this year have extended 3D TSV work to MEMS and CMOS image sensors (STMicroelectronics), stacked DRAM memories (Elpida), and backside illumination for camera sensors (Sony). So pervasive is the activity going on in 3D ICs and TSVs that the firm predicts that “new applications such as HB-LED silicon modules, solar and power components are also at the point to catch the 3D TSV trend.”
The biggest immediate issue for broader 3D IC/TSV adoption is supply chain and infrastructure readiness as well as cost. With many implementation scenarios identified for front-end, mid-end, back-end (e.g., via first, middle, last, or after bonding), it's still unclear who will step forward to invest and have the ownership of the different 3D TSV process steps.
To enable shorter interconnect lengths and higher I/O density along with more functionality, Applied Materials’ new Producer InVia dielectric deposition (CVD) system targets via-first and via-middle through-silicon via (TSV) integration applications. The new technology enables the deposition of the oxide liner film layer in high-aspect ratio (HAR) TSV structures. Applied’s global product marketing manager, Kedar Sapre, told Advanced Packaging Magazine that 80% of the company’s customers are doing a via-middle application, which, he notes, offers the greatest flexibility.
Manufacturers are currently considering a wide variety of 3-D integration schemes that present an equally broad range of TSV etch requirements. Critical factors for the etch process in 3D IC manufacturing are the ability to etch a variety of materials within the same chamber (in situ), using both conventional and special techniques for deep silicon etching, while maintaining excellent profile control and across-wafer uniformity. Plasma etch technology, which has been used extensively for deep silicon etching in memory devices and MEMS production, is well suited for TSV creation. The 2300 Syndion etch system from Lam Research is based on the company’s patented TCP technology and the 2300® Versys® Kiyo® conductor etch system. The Syndion system provides a flexible solution to address multiple TSV etch applications, supporting both conventional etching and the Bosch process. Tight and repeatable profile control assures that TSVs can be successfully implemented for a variety of 3-D IC schemes. The Syndion chamber can etch multiple materials in situ – including silicon, dielectrics, and conducting films – thereby addressing multiple TSV etch requirements.
Alchimer, on the other hand, believes that chemical and physical vapor deposition techniques show basic shortcomings and impose high capital investments, holding back the industry-wide adoption of 3D-IC solutions. They see a molecular engineering technology process called Electrografting (eG™) as a means to deliver high-quality films for high-aspect-ratio TSVs at a reduced cost as compared to conventional dry methods. Electrografting uses a wet process technique to generate surface-initiated conformal films which are thin, continuous, adherent and uniform.
EV Group sees advanced wafer alignment and wafer bonding techniques as an enabling solution for stacking of wafers and three-dimensional integration of devices. Wafer-to-wafer bond aligners support micron-level face-to-face alignment for 3D interconnects. The company’s SmartView Aligner offers a proprietary method for micron level face-to-face wafer level alignment. This alignment technique is key to achieving the required accuracy in multiple wafer stacking for leading edge technologies. SmartView technology combined with EV Group’s Gemini wafer bonding systems allows stacking of wafers through face-to-face alignment and subsequent permanent bonding to form electrical or optical interconnects between wafers.
The SUSS MicroTec engineers see material flexibility specifically for temporary bonding of device wafers to carrier wafers as critical considerations for TSV manufacturing. They address this by aligning their equipment design and capability with the materials suppliers for temporary adhesives. The most common materials; 3M, Brewer, Thin Materials, and Hitachi DuPont; can be run on the SUSS XBC300 Wafer Bonder platform. Another theme related to TSV challenges today are device testing. 3D integration requires wafer probers specifically designed for testing 3D structures and TSV testing. Due to yield concerns, the use of Known Good Die is required. Cascade Microtech offers the PA300PS-3D probe system.
3D IC Metrology
The market for metrology and inspection equipment for 3D TSVs also is growing. “Our analysis shows that while the overall equipment market will grow at a compound annual growth rate of nearly 60% between 2008 and 2013, the metrology/inspection sector is expected to grow nearly 80%,” noted Dr. Robert Castellano, president of The Information Network. “On the device side, TSVs for MEMS is expected to grow nearly 100% in this time frame.”
Scanning Acoustic Microscopy, commonly referred to as SAM or SAT (Scanning Acoustic Tomography) is one technique anticipated to facilitate TSV manufacturing. The ECHO SAM from Sonix can detect defects as small as 0.05 micron and is an excellent tool for bump detection, stacked die (3D packaging) inspection, complex flipchip inspection and more traditional plastic packages. Optical metrology is also necessary for TSV process control. Zygo has introduced a Nano 3D series specifically for 3D bump metrology that offers high throughput and accuracy for measurement of volume, height, diameters, areas, and coplanarity of C4 round and coined (flattened) bumps as well as chip capacitor pads in unlimited sizes of C4 area and package size.
According to Yole, it is also astonishing to notice the rapid evolution of 3D thinking within the IC community. Two years ago, the unceasing question was, “Why 3D?” Today, moving forward with the concrete implementation of the technology, questions are “When 3D?” and “”How 3D?”
To learn more about the latest advances in 3DIC, visit all these companies at SEMICON West 2010. And, don’t miss the SEMICON West 2010 TechXPOT session on 3D IC/TSV technology, entitled, Bridging the Gap, on Tuesday, July 13, 10:30am-12:30pm, North Hall.