EUV Lithography: Ready for 2015?
EUV Lithography: Ready for 2015?
The industry is counting on EUV – Will it be ready In time?
By David Lammers
June 3, 2010 – Semiconductor companies are counting on EUV lithography to be ready by 2015 for high-volume manufacturing. With early adopters now using high-k dielectrics in the gate stack, the next grand challenge facing the chip industry is to transition to EUV for the critical layers of memory and logic chips made roughly five years from now. While ASML is making impressive progress – the Dutch company expects to ship six EUV NXT: 3100 scanners beginning later this year for process development – questions remain whether the source and mask infrastructures will be fully ready in time.
To make EUV attractive for volume manufacturing, throughput needs to approach the 150-180 wafers-per-hour levels of today’s immersion 193 nm immersion scanners. For EUV, throughput largely depends on source power, which determines the ability to generate enough of the 13.4 nm-wavelength photons to quickly expose circuit patterns.
Cymer Inc. (San Diego) and Gigaphoton Inc. (Oyama, Japan) are providing laser-produced plasma (LPP) sources, with Cymer supplying ASML with the sources for its EUV scanners. Other companies are developing dipole-produced plasma (DPP), though their demonstrations have been less public.
Will LPP sources be powerful enough to meet EUV’s throughput goals? Nigel Farrar, vice president of strategic applications at Cymer, said observers should be careful to distinguish between “raw” EUV source power and “clean” power at the intermediate focus. Raw power is what the source delivers before it is filtered for spectral purity and dose control.
EUV lithography uses a series of reflective optics and 13.4 nm wavelength light to image patterns on a wafer. (Source: Obert Wood, GLOBALFOUNDRIES, at Sematech Litho Forum)
Farrar said Cymer is pursuing several methods to sharply boost source power this year and next. The source power’s efficiency is improved if the laser is timed to hit smaller tin droplets, measuring 30 micrometers in diameter. And Farrar said the pulse length of the CO2 laser will need to approach 400 ms if the sensitivity of the resist can be improved to 10 mJ, but even longer bursts will be needed if the resist sensitivity is in the 30 mJ range. Debris mitigation is another challenge, as the tin debris can damage the expensive collector mirrors and shorten the working lifetime of the optics. Farrar said the company has proprietary solutions for this problem.
Cymer remains confident it can meet the roadmap set by ASML. “Our intent,” Farrar said, “is to upgrade to the full power requirements, starting with a 100W source for the ASML 3100 scanners.” Asked about the roadmap for the NXT: 3300 EUV scanners which ASML plans to sell beginning in 2012 for full chip manufacturing, Farrar said “we are heavily in the co-design stage with ASML on the NXT: 3300.”
Nikon Corp. is also developing an EUV scanner, set to debut in 2014-15 for high-volume manufacturing at the 15 nm node, said Toshikazu Umatate, a vice president at Nikon’s lithography unit.
Another technical challenge facing EUV lithography revolves around the masks, which in EUV’s case are MoSi multi-coated reflective surfaces with the patterns deposited conventionally on the mask blanks. If any particles stick to the multi-coatings of silicon and molybdenum as they are deposited, the resulting bump on the mask blank can make it unusable. Some defects are repairable with ion beam milling. One encouraging sign is that Intel Corp.’s mask shop has created a defect-free EUV mask by positioning the pattern in places where there are no pits or bumps, and completely repairing other defects.
At the recent Sematech Litho Forum in New York City, Obert Wood, the GLOBALFOUNDRIES staff member who is the EUV project leader at the IBM-led Fishkill Semiconductor Alliance, said: “The EUV source power and mask defects are not there yet. But with EUV we can resolve spaces of 20 nm between the contact holes with near-perfect alignment.”
It is the sheer technical power of EUV, and its ability to be extended with up to 0.7 NA optics and 6.8 nm wavelength radiation, that has caused most of the industry’s lithography R&D budget to go towards EUV. Comparing what is possible with double patterning using 193 nm immersion scanners, Wood said that while double-patterning will work for the 40 nm half-pitch generation, it runs into resolution problems at the next technology generation. Particularly for DRAMs, with their two-dimensional structures, EUV may be a necessity on both technological and cost considerations.
EUV Throughput: EUV throughput depends on sharply boosting the source power over the next three years. (Source: Obert Wood, GlobalFoundries, at Sematech Litho Forum)
John Warlaumont, vice president of advanced technology at Sematech’s Albany site, said at the Litho Forum that in previous years the semiconductor industry has debated whether EUV or other options such as direct-write E-beam would carry the industry in 2015 and beyond. “There is less of that now, and more of a discussion about how to make EUV a success. When chip companies look at double-patterning, there are cost and extendibility issues, so companies want to pull EUV in. But sooner doesn’t come for free, and the question now is how to get the whole industry to pay for it,” Warlaumont said.
Lithography at SEMICON West 2010
Don't miss Advanced Lithography, Wednesday, July 14, 2:00pm–4:30pm, at the TechXPOT located in North Hall at Moscone Center. Admission to all technical sessions at the TechXPOT are free to registered SEMICON West attendees.
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