E-Beam Lithography Seeks Investment Boost

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E-Beam Lithography Seeks Investment Boost

With zero mask costs and the ability to create ultra-dense patterns, what’s not to like about electron beam lithography?

By David Lammers

May 27, 2010 – With the semiconductor industry facing worrying cost increases for double-patterning with immersion scanners, coupled with concerns that the mask and source infrastructure for EUV lithography may be lagging, Direct-write e-beam (DWEB) is receiving continuing interest. Direct-write e-beam also goes by the trendy moniker ML2 (for Mask-Less Lithography). By exposing a resist directly with multiple low-energy e-beams, the approach minimizes the Coulombic forces that tend to scatter electrons, thus realizing highly accurate pattern creation.

Several companies are making serious direct write e-beam development efforts, including KLA-Tencor, (Milpitas, Calif.), JEOL (Tokyo), Mapper Lithography (Delft, Netherlands), PARAM Corp. (Tokyo), Vistec (Vienna, Austria), and others. E-beam technology is relatively mature and low-cost, so companies can create workable DWEB systems at far less cost than, say, EUV lithography.

Developing a low-throughput DWEB system is old hat: IBM and many other companies have used them for years to develop prototypes. The challenge is scaling up to the thousands of e-beams required to achieve high throughputs in semiconductor manufacturing factories. Today’s 193 nm immersion optical scanners can expose >180 wph in single patterning mode, and >100 wph for double patterning. Those systems include high-speed stages and alignment sub-systems that contribute to the roughly $60M cost of a leading edge immersion scanner.

Taking DWEB from prototyping to commercial production, however, is a long leap. Burn Lin, senior director of the nanopatterning technology division at Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan), is an advocate of DWEB technology, but adds that the technology badly needs more semiconductor companies to invest in the approach.

TSMC may provide the best test bed for comparing DWEB (or as Lin calls it, MEBDW, indicating multiple beams). The foundry has purchased a “pre-alpha” DWEB tool from Mapper, with 110 beams. And later this year, it will take possession of an NXT:3100 system from ASML, an early EUV scanner that has a 60 wph goal.

Direct-write electron-beam (DWEB) lithography does not require a mask, but faces throughput challenges. (Source: Burn Lin, 2009 IEDM Short Course)


Lin acknowledges that to go from 110 beams on the pre-alpha Mapper tool to 13,000 beams on the first commercial Mapper system will require much more investment. But while EUV must wrestle with mask and optics issues to continue to improve, DWEB can take advantage of Moore’s Law. His reasoning is based on the fundamental challenge facing DWEB: data handling. Taking a full-field chip, 26 mm wide, and dividing the patterns by many thousands of e-beams, requires data path handling based on computational power and storage capabilities. Lin’s argument is that DWEB will be aided by the very transistor scaling it will help support. “Compute power and storage is getting very cheap,” Lin said.

Lin, who goaded the lithography industry into using immersion techniques, is one powerful voice supporting DWEB. Another is Yan Borodovsky, an Intel fellow and lithography researcher. Beginning at last year’s SEMICON West and continuing at two lithography forums this year, Borodovsky has been saying that DWEB might be used to delineate the ends of patterns created by high-throughput immersion scanners. By combining DWEB and 193i scanners, the industry could manage to continue Moore’s Law scaling while the EUV scanners achieve the “affordable and available” criteria that Intel demands of its lithography tools.

Mapper co-founder Bert Jan Kampherbeek said he believes Intel may buy a high-throughput Mapper machine once the 13k-beam machine is ready. To get Intel and other chip companies to support DWEB, “we have to show results,” Kampherbeek said. Meanwhile, French R&D consortium LETI, as well as TSMC and STMicroelectronics, continue to work with the two existing Mapper 110-beam tools. The 110-beam system has been used to create 22 nm half-pitch dense holes, and other e-beam systems have created 5 nm lines and spaces at the Delft University of Technology.

“Intel at least is talking about it,” Kampherbeek said, adding that “We need to get more IC companies involved. That won’t happen overnight; it will take time. But I am optimistic.”

Mapper Lithography plans to scale up to 13k beams for 10 wph throughput. (Source: Burn Lin, 2009 IEDM Short Course)


Lithography at SEMICON West 2010

Don't miss Advanced Lithography, Wednesday, July 14, 2:00pm–4:30pm, at the TechXPOT located in North Hall at Moscone Center. Admission to all technical sessions at the TechXPOT are free to registered SEMICON West attendees.