Industry Leaders Outline 3D TSV Revolution
Industry experts from ASE Group, Gartner, IMEC, Qualcomm, AVIZA, Synopsys, and Verigy discussed the key TSV drivers, manufacturing challenges, methods of implementation, and test strategies required to ensure a successful adoption of this emerging interconnect technology at the CTO Forum held in conjunction with SEMICON Taiwan.
Through Silicon Via (TSV) technology is already making an impact in many equipment and materials suppliers revenues in 2007. According to Yole Development, 3D-TSC wafers could account for as much as 6% of the total semiconductor industry and 25% of the memory market by 2015. Equipment and materials markets for manufacturing TSV ICs are projected to reach $1 billion by 2013 and 2015, respectively.
The Forum started off with Dr. Ho-Ming Tong, Chairman of SEMI Packaging & Test Committee and GM and Chief R&D Officer, ASE Group, giving an overview of TSV technology and explaining the 3 types of TSV; Die on Die (or Wafer), thru mold compound and thru substrate. This presentation was followed by Dr William Chen, Senior Advisor for ASE Group and IEEE Fellow President, IEEE CPMT Society providing a review of the ITRS roadmap. Dr. Chen explained that the packaging roadmap has constantly underestimated the packaging integration speed and pace. He predicted that 100% of the packaging materials used today will change this decade and that in the next decade the materials will transition again.
Other presentation at the Forum discussed the overall TSV market, including applications and market size and growth estimates. Jim Walker, Research Vice President from Gartner stressed that with the convergence of computing, mobility and content comes the ever increasing need for the convergence of silicon die, package and board level design. “To meet today’s requirements, a complete system level design is now required,” he said.
Jim used a couple of recent high profile examples to support his claim; the Microsoft XBOX and Nvidia GPU thermal problems. Jim also predicted that the next driver of TSV interconnects will be memory stacks that will be in production late next year.
Dr. Eric Beyne completed the morning session with a technology overview highlighting the various TSV approaches as well as the requirements for cost effective implementation.
The afternoon session kicked off with Tom Gregorich, Vice President from Qualcomm providing a review of the handset OEM requirements over the last ten years and then transitioned to current needs for TSV adoption. Tom described the first OEM handset requirement as “cost, cost, cost” followed by a decade of “cost + size” which has now transitioned to “cost+size+performance”. This last requirement is supported by the soon to be released handset complete with a 1Ghz processor. Tom cited many gaps to TSV adoption, some of which were post-wafer processing infrastructure, availability of KGD, standardization of interfaces, 3D EDA tools, and thermal management. Kevin Crofton, Vice President &GM, PVD, CVD & Etch Product Groups at AVIZA followed with a view of the TSV landscape, citing that 300mm wafer TSV processing equipment technology is available, but etch, barrier and seed-though challenges still exist with via shape, undercutting and scalloping. Kevin estimated that “Via first” will be adopted within 5-7 yrs.
The later half of the afternoon was completed by a discussion on EDA tools, Test Strategies and finally a panel discussion staffed with the day’s presenters. The EDA discussion was led by Dr. Charles Chiang, SNPS Scientist, Synopsys. Dr. Chiang explained the need for software design tool companies to fully understand the issues involved with modeling the complete package. However, most tools are still in the planning stages and the basis for driving these projects will be the economics of the market. In the meantime, EDA companies continue to monitor and collaborate with the industry to fully understand the requirements. Mr. Wilhelm Radermacher, Senior Director, Mixed Signal &RF Solutions, Semiconductor Test, at Verigy wrapped up the presentations by providing a suggested test strategy for 3D ICs using TSV technology. Mr. Radermacher suggested using the lessons learned over the last 10 years with SiP. This led to his suggestion of combining (at wafer probe) DFT and ATE which he defined as a class called Pretty Good Die (PGD). This would be coupled with a system level final test to ensure overall high quality fault coverage as well as controlling cost.