Advanced Processes and Materials at 32nm and 22nm Featured at SEMICON West

Advanced Processes and Materials at 32nm and 22nm Featured at SEMICON West

“Things are changing so much faster now, in this current period, than they did for many decades,” said Intel Chief Technology Officer, Justin Rattner, in an interview earlier this year with the Associated Press. “The pace of change is accelerating because we’re approaching a number of different physical limits at the same time.”

Overcoming these limits will be the objective of the device scaling programs at SEMICON West 2008. From exhibitor demonstrations and new product displays to the free Device Scaling TechXPOT, meeting the challenges of Moore’s Law will be evident throughout this year’s SEMICON West—the oldest, most international, and most influential industry event.

TechXPOTS are SEMICON West’s “show-within-a-show” concept where perspectives on the current and future state of technology are presented in free forums intermixed with exhibitors on the show floor. Attendees can attend the TechXPOT presentations and take the ideas and concepts directly to exhibitors for discussions about product development and implementation.

The Device Scaling TechXPOT (one of three TechXPOTS) will address the critical issues in achieving Moore Law. It will include sessions on “Advanced Processes and Materials for New Devices” on Tuesday, July 15 from 10:30am–1:00pm and “Lithography for 22nm: Will We Have a Viable Solution—and Will We Be Able to Afford it?” that afternoon from 3:00pm–5:00pm.

The Advanced Processes session will address current and emerging requirements for new materials like high-k gate and capacitor dielectrics, low-k interlayer dielectrics, and engineered substrates. This session will feature presentations by device makers, equipment manufacturers, R&D labs, and materials suppliers describing these new technologies and how they have been integrated into production.

Among the presentations given will be Hi-Mobility Channels by Prashant Majhi, ISMI / Sematech. Mobility, or the ability of a charge to move from source to drain, is one of the most active fields of research today. Many of the emerging solutions promise 10X reduction in power with 50% increase in speed, combined with better integration benefits.

Another presentation in the Advanced Processes session will cover the latest developments in the integration of III-V compounds into CMOS technology. James Fiorenza from Amber Wave will discuss Ge & III-V Hetero Integration for MOSFETs. Universities, ISMI and institutions like IMEC have been engaged in considerable research in indium antimonide, gallium arsenide, indium gallium arsenide, germanium and other III-V compounds that are expected by many to make significant inroads in as little two years.

Atul Athalye, director of technology, electronic materials at Linde Electronics will join the session to present Novel Precursor Formulations & Delivery Methods for Advanced ALD Applications. Linde has been developing new precursor formulations to broaden the materials choices for atomic layer deposition (ALD). Some of the benefits realized by Linde in high-k applications include: improved process stability, higher precursor utilization, purer films, and excellent process control.

The final presentation in the Advanced Processes session will come from Martin Green, leader of NIST’s Functional Properties Group, on Applications of Combinatorial Methodologies to the Advanced Gate Stack. NIST has established the National Computational Methods Center (NCMC) to promote industrial adaptation of combinatorial and high-throughput measurement methods that serve to accelerate the discovery, development, and optimization of innovative materials. This field is making increasing contributions to the semiconductor industry, especially in high k/metal gate stacks.

Tuesday afternoon’s “Lithography for 22nm” session will feature perspectives from industry luminaries representing design, layout, exposure tooling, and manufacturing integration. The 22 nm node, expected to be reached by semiconductor companies in the 2011-2012 timeframe, is likely to be achieved through double patterning using 193-nm dry or water-based immersion lithography tools. The discussion will explore: Is source-mask optimization really ready for 22nm? Will such a complex optical solution preserve the desirable features of optical lithography (high throughput at low cost with good reliability)? Some observers predict the 22nm lithography solution may present severe layout restrictions? Can our industry thrive if we take layout creativity away from designers? In this session, speakers from ASML, AMD, TSMC, Carnegie Mellon, PDF Solutions, and Cadence will share their views on the technical feasibility and financial viability of a patterning solution for 22nm.

The Device Scaling TechXPOT also has “Materials and Equipment Challenges for 32nm and 22nm” on the agenda for Wednesday, July 16. This session will look at the next 5–8 years and address the replacement for traditional CMOS devices if traditional scaling advances prove limited. Dr. John Chen, VP of Technology at Nvidia will outline the performance requirements that are driving the demand for new technology. Several device makers will describe the challenges they face in both logic and memory to meet these demands. Presentations from from IMEC, ISMI and SRC will focus on the R&D efforts to develop the new devices, materials and technologies needed

The Wednesday morning session will explore fab agility and productivity and the increased need for new metrology and process control solutions.

For more information and a detailed scheduled on all the programs at SEMICON West that address advanced wafer processing, click here. For information on all the programs, exhibitors and special events at SEMICON West, visit www.semiconwest.org